Lines Matching refs:x12
329 # CHECK: cmn x12, x13, lsr #0
379 # CHECK: cmp x12, x13, lsr #0
434 # CHECK: {{sub x12, xzr|neg x12}}, x11, asr #31
484 # CHECK: {{subs x12, xzr|negs x12}}, x11, asr #31
1027 0x12 0x08 0xc0 0x5a
1060 0x12 0x5e 0xdf 0x9a
1167 # CHECK: smaddl xzr, w10, w11, x12
1178 # CHECK: smsubl xzr, w10, w11, x12
1189 # CHECK: umaddl xzr, w10, w11, x12
1200 # CHECK: umsubl xzr, w10, w11, x12
1232 # CHECK: mul x12, x13, x14
1242 0xf1 0x7f 0x12 0x9b
1528 # FP16: fcvtzs x12, h30, #45
1542 # CHECK: fcvtzs x12, s30, #45
1556 # CHECK: fcvtzs x12, d30, #45
1570 # FP16: fcvtzu x12, h30, #45
1584 # CHECK: fcvtzu x12, s30, #45
1598 # CHECK: fcvtzu x12, d30, #45
1702 # FP16: fcvtps x12, h20
1720 # FP16: fcvtzs x12, h13
1756 # CHECK: fcvtps x12, s20
1774 # CHECK: fcvtzs x12, s13
1810 # CHECK: fcvtps x12, d20
1828 # CHECK: fcvtzs x12, d13
1923 0xe8 0x7f 0x12 0x08
1943 #CHECK: stxp wzr, x27, x9, [x12]
2020 # CHECK: sturh wzr, [x12, #255]
2031 # CHECK: ldur xzr, [x12, #255]
2051 # CHECK: stur h12, [x12, #-1]
2063 # CHECK: ldur s7, [x12, #-1]
2095 # CHECK: str w21, [x12], #-256
2098 # CHECK: str x19, [x12], #-256
2121 # CHECK: ldr w21, [x12], #-256
2124 # CHECK: ldr x19, [x12], #-256
2134 # CHECK: ldrsb x19, [x12], #-256
2137 # CHECK: ldrsh x19, [x12], #-256
2140 # CHECK: ldrsw x19, [x12], #-256
2153 # CHECK: ldrsb w19, [x12], #-256
2156 # CHECK: ldrsh w19, [x12], #-256
2253 # CHECK: str w21, [x12, #-256]!
2256 # CHECK: str x19, [x12, #-256]!
2279 # CHECK: ldr w21, [x12, #-256]!
2282 # CHECK: ldr x19, [x12, #-256]!
2292 # CHECK: ldrsb x19, [x12, #-256]!
2295 # CHECK: ldrsh x19, [x12, #-256]!
2298 # CHECK: ldrsw x19, [x12, #-256]!
2311 # CHECK: ldrsb w19, [x12, #-256]!
2314 # CHECK: ldrsh w19, [x12, #-256]!
2390 # CHECK: sttrh wzr, [x12, #255]
2401 # CHECK: ldtr xzr, [x12, #255]
2424 # CHECK: ldr x30, [x12, #32760]
2603 # CHECK: ldr x12, [x28, xzr, sxtx]
2847 0xee 0x81 0x1 0x12
2848 0xac 0xad 0xa 0x12
2849 0xeb 0x87 0x0 0x12
2872 # CHECK: orr x11, x12, #0x8000000000000fff
2885 # CHECK: and x12, x13, #0xffc3ffc3ffc3ffc3
2999 0x42 0x9a 0x80 0x12
3157 # CHECK: {{sys #3, c7, c4, #1|dc zva}}, x12
3175 # CHECK: msr {{teecr32_el1|TEECR32_EL1}}, x12
3176 # CHECK: msr {{osdtrrx_el1|OSDTRRX_EL1}}, x12
3177 # CHECK: msr {{mdccint_el1|MDCCINT_EL1}}, x12
3178 # CHECK: msr {{mdscr_el1|MDSCR_EL1}}, x12
3179 # CHECK: msr {{osdtrtx_el1|OSDTRTX_EL1}}, x12
3180 # CHECK: msr {{dbgdtr_el0|DBGDTR_EL0}}, x12
3181 # CHECK: msr {{dbgdtrtx_el0|DBGDTRTX_EL0}}, x12
3182 # CHECK: msr {{oseccr_el1|OSECCR_EL1}}, x12
3183 # CHECK: msr {{dbgvcr32_el2|DBGVCR32_EL2}}, x12
3184 # CHECK: msr {{dbgbvr0_el1|DBGBVR0_EL1}}, x12
3185 # CHECK: msr {{dbgbvr1_el1|DBGBVR1_EL1}}, x12
3186 # CHECK: msr {{dbgbvr2_el1|DBGBVR2_EL1}}, x12
3187 # CHECK: msr {{dbgbvr3_el1|DBGBVR3_EL1}}, x12
3188 # CHECK: msr {{dbgbvr4_el1|DBGBVR4_EL1}}, x12
3189 # CHECK: msr {{dbgbvr5_el1|DBGBVR5_EL1}}, x12
3190 # CHECK: msr {{dbgbvr6_el1|DBGBVR6_EL1}}, x12
3191 # CHECK: msr {{dbgbvr7_el1|DBGBVR7_EL1}}, x12
3192 # CHECK: msr {{dbgbvr8_el1|DBGBVR8_EL1}}, x12
3193 # CHECK: msr {{dbgbvr9_el1|DBGBVR9_EL1}}, x12
3194 # CHECK: msr {{dbgbvr10_el1|DBGBVR10_EL1}}, x12
3195 # CHECK: msr {{dbgbvr11_el1|DBGBVR11_EL1}}, x12
3196 # CHECK: msr {{dbgbvr12_el1|DBGBVR12_EL1}}, x12
3197 # CHECK: msr {{dbgbvr13_el1|DBGBVR13_EL1}}, x12
3198 # CHECK: msr {{dbgbvr14_el1|DBGBVR14_EL1}}, x12
3199 # CHECK: msr {{dbgbvr15_el1|DBGBVR15_EL1}}, x12
3200 # CHECK: msr {{dbgbcr0_el1|DBGBCR0_EL1}}, x12
3201 # CHECK: msr {{dbgbcr1_el1|DBGBCR1_EL1}}, x12
3202 # CHECK: msr {{dbgbcr2_el1|DBGBCR2_EL1}}, x12
3203 # CHECK: msr {{dbgbcr3_el1|DBGBCR3_EL1}}, x12
3204 # CHECK: msr {{dbgbcr4_el1|DBGBCR4_EL1}}, x12
3205 # CHECK: msr {{dbgbcr5_el1|DBGBCR5_EL1}}, x12
3206 # CHECK: msr {{dbgbcr6_el1|DBGBCR6_EL1}}, x12
3207 # CHECK: msr {{dbgbcr7_el1|DBGBCR7_EL1}}, x12
3208 # CHECK: msr {{dbgbcr8_el1|DBGBCR8_EL1}}, x12
3209 # CHECK: msr {{dbgbcr9_el1|DBGBCR9_EL1}}, x12
3210 # CHECK: msr {{dbgbcr10_el1|DBGBCR10_EL1}}, x12
3211 # CHECK: msr {{dbgbcr11_el1|DBGBCR11_EL1}}, x12
3212 # CHECK: msr {{dbgbcr12_el1|DBGBCR12_EL1}}, x12
3213 # CHECK: msr {{dbgbcr13_el1|DBGBCR13_EL1}}, x12
3214 # CHECK: msr {{dbgbcr14_el1|DBGBCR14_EL1}}, x12
3215 # CHECK: msr {{dbgbcr15_el1|DBGBCR15_EL1}}, x12
3216 # CHECK: msr {{dbgwvr0_el1|DBGWVR0_EL1}}, x12
3217 # CHECK: msr {{dbgwvr1_el1|DBGWVR1_EL1}}, x12
3218 # CHECK: msr {{dbgwvr2_el1|DBGWVR2_EL1}}, x12
3219 # CHECK: msr {{dbgwvr3_el1|DBGWVR3_EL1}}, x12
3220 # CHECK: msr {{dbgwvr4_el1|DBGWVR4_EL1}}, x12
3221 # CHECK: msr {{dbgwvr5_el1|DBGWVR5_EL1}}, x12
3222 # CHECK: msr {{dbgwvr6_el1|DBGWVR6_EL1}}, x12
3223 # CHECK: msr {{dbgwvr7_el1|DBGWVR7_EL1}}, x12
3224 # CHECK: msr {{dbgwvr8_el1|DBGWVR8_EL1}}, x12
3225 # CHECK: msr {{dbgwvr9_el1|DBGWVR9_EL1}}, x12
3226 # CHECK: msr {{dbgwvr10_el1|DBGWVR10_EL1}}, x12
3227 # CHECK: msr {{dbgwvr11_el1|DBGWVR11_EL1}}, x12
3228 # CHECK: msr {{dbgwvr12_el1|DBGWVR12_EL1}}, x12
3229 # CHECK: msr {{dbgwvr13_el1|DBGWVR13_EL1}}, x12
3230 # CHECK: msr {{dbgwvr14_el1|DBGWVR14_EL1}}, x12
3231 # CHECK: msr {{dbgwvr15_el1|DBGWVR15_EL1}}, x12
3232 # CHECK: msr {{dbgwcr0_el1|DBGWCR0_EL1}}, x12
3233 # CHECK: msr {{dbgwcr1_el1|DBGWCR1_EL1}}, x12
3234 # CHECK: msr {{dbgwcr2_el1|DBGWCR2_EL1}}, x12
3235 # CHECK: msr {{dbgwcr3_el1|DBGWCR3_EL1}}, x12
3236 # CHECK: msr {{dbgwcr4_el1|DBGWCR4_EL1}}, x12
3237 # CHECK: msr {{dbgwcr5_el1|DBGWCR5_EL1}}, x12
3238 # CHECK: msr {{dbgwcr6_el1|DBGWCR6_EL1}}, x12
3239 # CHECK: msr {{dbgwcr7_el1|DBGWCR7_EL1}}, x12
3240 # CHECK: msr {{dbgwcr8_el1|DBGWCR8_EL1}}, x12
3241 # CHECK: msr {{dbgwcr9_el1|DBGWCR9_EL1}}, x12
3242 # CHECK: msr {{dbgwcr10_el1|DBGWCR10_EL1}}, x12
3243 # CHECK: msr {{dbgwcr11_el1|DBGWCR11_EL1}}, x12
3244 # CHECK: msr {{dbgwcr12_el1|DBGWCR12_EL1}}, x12
3245 # CHECK: msr {{dbgwcr13_el1|DBGWCR13_EL1}}, x12
3246 # CHECK: msr {{dbgwcr14_el1|DBGWCR14_EL1}}, x12
3247 # CHECK: msr {{dbgwcr15_el1|DBGWCR15_EL1}}, x12
3248 # CHECK: msr {{teehbr32_el1|TEEHBR32_EL1}}, x12
3249 # CHECK: msr {{oslar_el1|OSLAR_EL1}}, x12
3250 # CHECK: msr {{osdlr_el1|OSDLR_EL1}}, x12
3251 # CHECK: msr {{dbgprcr_el1|DBGPRCR_EL1}}, x12
3252 # CHECK: msr {{dbgclaimset_el1|DBGCLAIMSET_EL1}}, x12
3253 # CHECK: msr {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}}, x12
3254 # CHECK: msr {{csselr_el1|CSSELR_EL1}}, x12
3255 # CHECK: msr {{vpidr_el2|VPIDR_EL2}}, x12
3256 # CHECK: msr {{vmpidr_el2|VMPIDR_EL2}}, x12
3257 # CHECK: msr {{sctlr_el1|SCTLR_EL1}}, x12
3258 # CHECK: msr {{sctlr_el2|SCTLR_EL2}}, x12
3259 # CHECK: msr {{sctlr_el3|SCTLR_EL3}}, x12
3260 # CHECK: msr {{actlr_el1|ACTLR_EL1}}, x12
3261 # CHECK: msr {{actlr_el2|ACTLR_EL2}}, x12
3262 # CHECK: msr {{actlr_el3|ACTLR_EL3}}, x12
3263 # CHECK: msr {{cpacr_el1|CPACR_EL1}}, x12
3264 # CHECK: msr {{hcr_el2|HCR_EL2}}, x12
3265 # CHECK: msr {{scr_el3|SCR_EL3}}, x12
3266 # CHECK: msr {{mdcr_el2|MDCR_EL2}}, x12
3267 # CHECK: msr {{sder32_el3|SDER32_EL3}}, x12
3268 # CHECK: msr {{cptr_el2|CPTR_EL2}}, x12
3269 # CHECK: msr {{cptr_el3|CPTR_EL3}}, x12
3270 # CHECK: msr {{hstr_el2|HSTR_EL2}}, x12
3271 # CHECK: msr {{hacr_el2|HACR_EL2}}, x12
3272 # CHECK: msr {{mdcr_el3|MDCR_EL3}}, x12
3273 # CHECK: msr {{ttbr0_el1|TTBR0_EL1}}, x12
3274 # CHECK: msr {{ttbr0_el2|TTBR0_EL2}}, x12
3275 # CHECK: msr {{ttbr0_el3|TTBR0_EL3}}, x12
3276 # CHECK: msr {{ttbr1_el1|TTBR1_EL1}}, x12
3277 # CHECK: msr {{tcr_el1|TCR_EL1}}, x12
3278 # CHECK: msr {{tcr_el2|TCR_EL2}}, x12
3279 # CHECK: msr {{tcr_el3|TCR_EL3}}, x12
3280 # CHECK: msr {{vttbr_el2|VTTBR_EL2}}, x12
3281 # CHECK: msr {{vtcr_el2|VTCR_EL2}}, x12
3282 # CHECK: msr {{dacr32_el2|DACR32_EL2}}, x12
3283 # CHECK: msr {{spsr_el1|SPSR_EL1}}, x12
3284 # CHECK: msr {{spsr_el2|SPSR_EL2}}, x12
3285 # CHECK: msr {{spsr_el3|SPSR_EL3}}, x12
3286 # CHECK: msr {{elr_el1|ELR_EL1}}, x12
3287 # CHECK: msr {{elr_el2|ELR_EL2}}, x12
3288 # CHECK: msr {{elr_el3|ELR_EL3}}, x12
3289 # CHECK: msr {{sp_el0|SP_EL0}}, x12
3290 # CHECK: msr {{sp_el1|SP_EL1}}, x12
3291 # CHECK: msr {{sp_el2|SP_EL2}}, x12
3292 # CHECK: msr {{SPSel|SPSEL}}, x12
3293 # CHECK: msr {{nzcv|NZCV}}, x12
3294 # CHECK: msr {{daif|DAIF}}, x12
3295 # CHECK: msr {{CurrentEL|CURRENTEL}}, x12
3296 # CHECK: msr {{SPSR_irq|SPSR_IRQ}}, x12
3297 # CHECK: msr {{SPSR_abt|SPSR_ABT}}, x12
3298 # CHECK: msr {{SPSR_und|SPSR_UND}}, x12
3299 # CHECK: msr {{SPSR_fiq|SPSR_FIQ}}, x12
3300 # CHECK: msr {{fpcr|FPCR}}, x12
3301 # CHECK: msr {{fpsr|FPSR}}, x12
3302 # CHECK: msr {{dspsr_el0|DSPSR_EL0}}, x12
3303 # CHECK: msr {{dlr_el0|DLR_EL0}}, x12
3304 # CHECK: msr {{ifsr32_el2|IFSR32_EL2}}, x12
3305 # CHECK: msr {{afsr0_el1|AFSR0_EL1}}, x12
3306 # CHECK: msr {{afsr0_el2|AFSR0_EL2}}, x12
3307 # CHECK: msr {{afsr0_el3|AFSR0_EL3}}, x12
3308 # CHECK: msr {{afsr1_el1|AFSR1_EL1}}, x12
3309 # CHECK: msr {{afsr1_el2|AFSR1_EL2}}, x12
3310 # CHECK: msr {{afsr1_el3|AFSR1_EL3}}, x12
3311 # CHECK: msr {{esr_el1|ESR_EL1}}, x12
3312 # CHECK: msr {{esr_el2|ESR_EL2}}, x12
3313 # CHECK: msr {{esr_el3|ESR_EL3}}, x12
3314 # CHECK: msr {{fpexc32_el2|FPEXC32_EL2}}, x12
3315 # CHECK: msr {{far_el1|FAR_EL1}}, x12
3316 # CHECK: msr {{far_el2|FAR_EL2}}, x12
3317 # CHECK: msr {{far_el3|FAR_EL3}}, x12
3318 # CHECK: msr {{hpfar_el2|HPFAR_EL2}}, x12
3319 # CHECK: msr {{par_el1|PAR_EL1}}, x12
3320 # CHECK: msr {{pmcr_el0|PMCR_EL0}}, x12
3321 # CHECK: msr {{pmcntenset_el0|PMCNTENSET_EL0}}, x12
3322 # CHECK: msr {{pmcntenclr_el0|PMCNTENCLR_EL0}}, x12
3323 # CHECK: msr {{pmovsclr_el0|PMOVSCLR_EL0}}, x12
3324 # CHECK: msr {{pmselr_el0|PMSELR_EL0}}, x12
3325 # CHECK: msr {{pmccntr_el0|PMCCNTR_EL0}}, x12
3326 # CHECK: msr {{pmxevtyper_el0|PMXEVTYPER_EL0}}, x12
3327 # CHECK: msr {{pmxevcntr_el0|PMXEVCNTR_EL0}}, x12
3328 # CHECK: msr {{pmuserenr_el0|PMUSERENR_EL0}}, x12
3329 # CHECK: msr {{pmintenset_el1|PMINTENSET_EL1}}, x12
3330 # CHECK: msr {{pmintenclr_el1|PMINTENCLR_EL1}}, x12
3331 # CHECK: msr {{pmovsset_el0|PMOVSSET_EL0}}, x12
3332 # CHECK: msr {{mair_el1|MAIR_EL1}}, x12
3333 # CHECK: msr {{mair_el2|MAIR_EL2}}, x12
3334 # CHECK: msr {{mair_el3|MAIR_EL3}}, x12
3335 # CHECK: msr {{amair_el1|AMAIR_EL1}}, x12
3336 # CHECK: msr {{amair_el2|AMAIR_EL2}}, x12
3337 # CHECK: msr {{amair_el3|AMAIR_EL3}}, x12
3338 # CHECK: msr {{vbar_el1|VBAR_EL1}}, x12
3339 # CHECK: msr {{vbar_el2|VBAR_EL2}}, x12
3340 # CHECK: msr {{vbar_el3|VBAR_EL3}}, x12
3341 # CHECK: msr {{rmr_el1|RMR_EL1}}, x12
3342 # CHECK: msr {{rmr_el2|RMR_EL2}}, x12
3343 # CHECK: msr {{rmr_el3|RMR_EL3}}, x12
3344 # CHECK: msr {{tpidr_el0|TPIDR_EL0}}, x12
3345 # CHECK: msr {{tpidr_el2|TPIDR_EL2}}, x12
3346 # CHECK: msr {{tpidr_el3|TPIDR_EL3}}, x12
3347 # CHECK: msr {{tpidrro_el0|TPIDRRO_EL0}}, x12
3348 # CHECK: msr {{tpidr_el1|TPIDR_EL1}}, x12
3349 # CHECK: msr {{cntfrq_el0|CNTFRQ_EL0}}, x12
3350 # CHECK: msr {{cntvoff_el2|CNTVOFF_EL2}}, x12
3351 # CHECK: msr {{cntkctl_el1|CNTKCTL_EL1}}, x12
3352 # CHECK: msr {{cnthctl_el2|CNTHCTL_EL2}}, x12
3353 # CHECK: msr {{cntp_tval_el0|CNTP_TVAL_EL0}}, x12
3354 # CHECK: msr {{cnthp_tval_el2|CNTHP_TVAL_EL2}}, x12
3355 # CHECK: msr {{cntps_tval_el1|CNTPS_TVAL_EL1}}, x12
3356 # CHECK: msr {{cntp_ctl_el0|CNTP_CTL_EL0}}, x12
3357 # CHECK: msr {{cnthp_ctl_el2|CNTHP_CTL_EL2}}, x12
3358 # CHECK: msr {{cntps_ctl_el1|CNTPS_CTL_EL1}}, x12
3359 # CHECK: msr {{cntp_cval_el0|CNTP_CVAL_EL0}}, x12
3360 # CHECK: msr {{cnthp_cval_el2|CNTHP_CVAL_EL2}}, x12
3361 # CHECK: msr {{cntps_cval_el1|CNTPS_CVAL_EL1}}, x12
3362 # CHECK: msr {{cntv_tval_el0|CNTV_TVAL_EL0}}, x12
3363 # CHECK: msr {{cntv_ctl_el0|CNTV_CTL_EL0}}, x12
3364 # CHECK: msr {{cntv_cval_el0|CNTV_CVAL_EL0}}, x12
3365 # CHECK: msr {{pmevcntr0_el0|PMEVCNTR0_EL0}}, x12
3366 # CHECK: msr {{pmevcntr1_el0|PMEVCNTR1_EL0}}, x12
3367 # CHECK: msr {{pmevcntr2_el0|PMEVCNTR2_EL0}}, x12
3368 # CHECK: msr {{pmevcntr3_el0|PMEVCNTR3_EL0}}, x12
3369 # CHECK: msr {{pmevcntr4_el0|PMEVCNTR4_EL0}}, x12
3370 # CHECK: msr {{pmevcntr5_el0|PMEVCNTR5_EL0}}, x12
3371 # CHECK: msr {{pmevcntr6_el0|PMEVCNTR6_EL0}}, x12
3372 # CHECK: msr {{pmevcntr7_el0|PMEVCNTR7_EL0}}, x12
3373 # CHECK: msr {{pmevcntr8_el0|PMEVCNTR8_EL0}}, x12
3374 # CHECK: msr {{pmevcntr9_el0|PMEVCNTR9_EL0}}, x12
3375 # CHECK: msr {{pmevcntr10_el0|PMEVCNTR10_EL0}}, x12
3376 # CHECK: msr {{pmevcntr11_el0|PMEVCNTR11_EL0}}, x12
3377 # CHECK: msr {{pmevcntr12_el0|PMEVCNTR12_EL0}}, x12
3378 # CHECK: msr {{pmevcntr13_el0|PMEVCNTR13_EL0}}, x12
3379 # CHECK: msr {{pmevcntr14_el0|PMEVCNTR14_EL0}}, x12
3380 # CHECK: msr {{pmevcntr15_el0|PMEVCNTR15_EL0}}, x12
3381 # CHECK: msr {{pmevcntr16_el0|PMEVCNTR16_EL0}}, x12
3382 # CHECK: msr {{pmevcntr17_el0|PMEVCNTR17_EL0}}, x12
3383 # CHECK: msr {{pmevcntr18_el0|PMEVCNTR18_EL0}}, x12
3384 # CHECK: msr {{pmevcntr19_el0|PMEVCNTR19_EL0}}, x12
3385 # CHECK: msr {{pmevcntr20_el0|PMEVCNTR20_EL0}}, x12
3386 # CHECK: msr {{pmevcntr21_el0|PMEVCNTR21_EL0}}, x12
3387 # CHECK: msr {{pmevcntr22_el0|PMEVCNTR22_EL0}}, x12
3388 # CHECK: msr {{pmevcntr23_el0|PMEVCNTR23_EL0}}, x12
3389 # CHECK: msr {{pmevcntr24_el0|PMEVCNTR24_EL0}}, x12
3390 # CHECK: msr {{pmevcntr25_el0|PMEVCNTR25_EL0}}, x12
3391 # CHECK: msr {{pmevcntr26_el0|PMEVCNTR26_EL0}}, x12
3392 # CHECK: msr {{pmevcntr27_el0|PMEVCNTR27_EL0}}, x12
3393 # CHECK: msr {{pmevcntr28_el0|PMEVCNTR28_EL0}}, x12
3394 # CHECK: msr {{pmevcntr29_el0|PMEVCNTR29_EL0}}, x12
3395 # CHECK: msr {{pmevcntr30_el0|PMEVCNTR30_EL0}}, x12
3396 # CHECK: msr {{pmccfiltr_el0|PMCCFILTR_EL0}}, x12
3397 # CHECK: msr {{pmevtyper0_el0|PMEVTYPER0_EL0}}, x12
3398 # CHECK: msr {{pmevtyper1_el0|PMEVTYPER1_EL0}}, x12
3399 # CHECK: msr {{pmevtyper2_el0|PMEVTYPER2_EL0}}, x12
3400 # CHECK: msr {{pmevtyper3_el0|PMEVTYPER3_EL0}}, x12
3401 # CHECK: msr {{pmevtyper4_el0|PMEVTYPER4_EL0}}, x12
3402 # CHECK: msr {{pmevtyper5_el0|PMEVTYPER5_EL0}}, x12
3403 # CHECK: msr {{pmevtyper6_el0|PMEVTYPER6_EL0}}, x12
3404 # CHECK: msr {{pmevtyper7_el0|PMEVTYPER7_EL0}}, x12
3405 # CHECK: msr {{pmevtyper8_el0|PMEVTYPER8_EL0}}, x12
3406 # CHECK: msr {{pmevtyper9_el0|PMEVTYPER9_EL0}}, x12
3407 # CHECK: msr {{pmevtyper10_el0|PMEVTYPER10_EL0}}, x12
3408 # CHECK: msr {{pmevtyper11_el0|PMEVTYPER11_EL0}}, x12
3409 # CHECK: msr {{pmevtyper12_el0|PMEVTYPER12_EL0}}, x12
3410 # CHECK: msr {{pmevtyper13_el0|PMEVTYPER13_EL0}}, x12
3411 # CHECK: msr {{pmevtyper14_el0|PMEVTYPER14_EL0}}, x12
3412 # CHECK: msr {{pmevtyper15_el0|PMEVTYPER15_EL0}}, x12
3413 # CHECK: msr {{pmevtyper16_el0|PMEVTYPER16_EL0}}, x12
3414 # CHECK: msr {{pmevtyper17_el0|PMEVTYPER17_EL0}}, x12
3415 # CHECK: msr {{pmevtyper18_el0|PMEVTYPER18_EL0}}, x12
3416 # CHECK: msr {{pmevtyper19_el0|PMEVTYPER19_EL0}}, x12
3417 # CHECK: msr {{pmevtyper20_el0|PMEVTYPER20_EL0}}, x12
3418 # CHECK: msr {{pmevtyper21_el0|PMEVTYPER21_EL0}}, x12
3419 # CHECK: msr {{pmevtyper22_el0|PMEVTYPER22_EL0}}, x12
3420 # CHECK: msr {{pmevtyper23_el0|PMEVTYPER23_EL0}}, x12
3421 # CHECK: msr {{pmevtyper24_el0|PMEVTYPER24_EL0}}, x12
3422 # CHECK: msr {{pmevtyper25_el0|PMEVTYPER25_EL0}}, x12
3423 # CHECK: msr {{pmevtyper26_el0|PMEVTYPER26_EL0}}, x12
3424 # CHECK: msr {{pmevtyper27_el0|PMEVTYPER27_EL0}}, x12
3425 # CHECK: msr {{pmevtyper28_el0|PMEVTYPER28_EL0}}, x12
3426 # CHECK: msr {{pmevtyper29_el0|PMEVTYPER29_EL0}}, x12
3427 # CHECK: msr {{pmevtyper30_el0|PMEVTYPER30_EL0}}, x12
3730 0xc 0x0 0x12 0xd5
3803 0xc 0x10 0x12 0xd5
4285 # CHECK: mrs x12, {{s3_7_c15_c1_5|S3_7_C15_C1_5}}
4288 # CHECK: msr {{s3_0_c15_c0_0|S3_0_C15_C0_0}}, x12
4302 # CHECK: tbz x12, #62, #0
4303 # CHECK: tbz x12, #62, #4
4304 # CHECK: tbz x12, #62, #-32768
4305 # CHECK: tbnz x12, #60, #32764