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Lines Matching refs:RegisterClasses

122   const auto &RegisterClasses = Bank.getRegClasses();  in runEnums()  local
123 if (!RegisterClasses.empty()) { in runEnums()
126 assert(RegisterClasses.size() <= 0xffff && in runEnums()
133 for (const auto &RC : RegisterClasses) in runEnums()
981 const auto &RegisterClasses = RegBank.getRegClasses(); in runMCDesc() local
989 for (const auto &RC : RegisterClasses) { in runMCDesc()
1029 for (const auto &RC : RegisterClasses) { in runMCDesc()
1074 << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, " in runMCDesc()
1138 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetHeader() local
1140 if (!RegisterClasses.empty()) { in runTargetHeader()
1141 OS << "namespace " << RegisterClasses.front().Namespace in runTargetHeader()
1144 for (const auto &RC : RegisterClasses) { in runTargetHeader()
1150 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n"; in runTargetHeader()
1174 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetDesc() local
1181 for (const auto &RC : RegisterClasses) { in runTargetDesc()
1190 for (const auto &RC : RegisterClasses) in runTargetDesc()
1216 if (!RegisterClasses.empty()) { in runTargetDesc()
1240 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size()); in runTargetDesc()
1242 BitVector MaskBV(RegisterClasses.size()); in runTargetDesc()
1244 for (const auto &RC : RegisterClasses) { in runTargetDesc()
1271 for (const auto &RC : RegisterClasses) { in runTargetDesc()
1286 for (const auto &RC : RegisterClasses) { in runTargetDesc()
1318 OS << "\nnamespace " << RegisterClasses.front().Namespace in runTargetDesc()
1321 for (const auto &RC : RegisterClasses) { in runTargetDesc()
1345 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; in runTargetDesc()
1350 for (const auto &RC : RegisterClasses) in runTargetDesc()
1388 if (RegisterClasses.size() < UINT8_MAX) in runTargetDesc()
1390 else if (RegisterClasses.size() < UINT16_MAX) in runTargetDesc()
1394 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; in runTargetDesc()
1395 for (const auto &RC : RegisterClasses) { in runTargetDesc()
1432 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n" in runTargetDesc()
1438 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n" in runTargetDesc()