Lines Matching refs:ModelDef
661 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel"); in FindWriteResources() local
662 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindWriteResources()
692 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindWriteResources()
713 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel"); in FindReadAdvance() local
714 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindReadAdvance()
744 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindReadAdvance()
1156 PrintFatalError(PM.ModelDef->getLoc(), "SchedMachineModel defines " in EmitProcessorModels()
1162 EmitProcessorProp(OS, PM.ModelDef, "IssueWidth", ','); in EmitProcessorModels()
1163 EmitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ','); in EmitProcessorModels()
1164 EmitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ','); in EmitProcessorModels()
1165 EmitProcessorProp(OS, PM.ModelDef, "LoadLatency", ','); in EmitProcessorModels()
1166 EmitProcessorProp(OS, PM.ModelDef, "HighLatency", ','); in EmitProcessorModels()
1167 EmitProcessorProp(OS, PM.ModelDef, "MispredictPenalty", ','); in EmitProcessorModels()
1170 (PM.ModelDef ? PM.ModelDef->getValueAsBit("PostRAScheduler") : false); in EmitProcessorModels()
1176 (PM.ModelDef ? PM.ModelDef->getValueAsBit("CompleteModel") : false); in EmitProcessorModels()