Lines Matching refs:ProcModel
91 void EmitProcessorResources(const CodeGenProcModel &ProcModel,
94 const CodeGenProcModel &ProcModel);
96 const CodeGenProcModel &ProcModel);
98 const CodeGenProcModel &ProcModel);
99 void GenSchedClassTables(const CodeGenProcModel &ProcModel,
367 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { in EmitStageAndOperandCycleData() local
369 if (!ItinsDefSet.insert(ProcModel.ItinsDef).second) in EmitStageAndOperandCycleData()
372 std::vector<Record*> FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU"); in EmitStageAndOperandCycleData()
376 const std::string &Name = ProcModel.ItinsDef->getName(); in EmitStageAndOperandCycleData()
386 std::vector<Record*> BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP"); in EmitStageAndOperandCycleData()
420 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { in EmitStageAndOperandCycleData() local
427 if (!ProcModel.hasItineraries()) in EmitStageAndOperandCycleData()
430 const std::string &Name = ProcModel.ItinsDef->getName(); in EmitStageAndOperandCycleData()
433 assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins"); in EmitStageAndOperandCycleData()
439 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; in EmitStageAndOperandCycleData()
600 void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, in EmitProcessorResources() argument
602 char Sep = ProcModel.ProcResourceDefs.empty() ? ' ' : ','; in EmitProcessorResources()
606 << ProcModel.ModelName << "ProcResources" << "[] = {\n" in EmitProcessorResources()
609 for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) { in EmitProcessorResources()
610 Record *PRDef = ProcModel.ProcResourceDefs[i]; in EmitProcessorResources()
626 PRDef->getValueAsDef("Super"), ProcModel); in EmitProcessorResources()
627 SuperIdx = ProcModel.getProcResourceIdx(SuperDef); in EmitProcessorResources()
649 const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) { in FindWriteResources() argument
662 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindWriteResources()
667 "defined for processor " + ProcModel.ModelName + in FindWriteResources()
676 for (Record *WR : ProcModel.WriteResDefs) { in FindWriteResources()
684 ProcModel.ModelName); in FindWriteResources()
692 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindWriteResources()
702 const CodeGenProcModel &ProcModel) { in FindReadAdvance() argument
714 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindReadAdvance()
719 "defined for processor " + ProcModel.ModelName + in FindReadAdvance()
728 for (Record *RA : ProcModel.ReadAdvanceDefs) { in FindReadAdvance()
736 ProcModel.ModelName); in FindReadAdvance()
744 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindReadAdvance()
801 void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, in GenSchedClassTables() argument
804 if (!ProcModel.hasInstrSchedModel()) in GenSchedClassTables()
831 TI->ProcIndices.end(), ProcModel.Index); in GenSchedClassTables()
848 SC.ProcIndices.end(), ProcModel.Index); in GenSchedClassTables()
860 if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) { in GenSchedClassTables()
874 for (Record *I : ProcModel.ItinRWDefs) { in GenSchedClassTables()
884 DEBUG(dbgs() << ProcModel.ModelName in GenSchedClassTables()
896 ProcModel); in GenSchedClassTables()
914 FindWriteResources(SchedModels.getSchedWrite(WS), ProcModel); in GenSchedClassTables()
931 ExpandProcResources(PRVec, Cycles, ProcModel); in GenSchedClassTables()
936 WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]); in GenSchedClassTables()
962 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel); in GenSchedClassTables()
1258 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { in EmitSchedModel() local
1259 GenSchedClassTables(ProcModel, SchedTables); in EmitSchedModel()