289 			AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;  in gfx6_compute_level()
291 			AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;  in gfx6_compute_level()
305 	surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];  in gfx6_compute_level()
326 		surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;  in gfx6_compute_level()
328 		surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;  in gfx6_compute_level()
392 	uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];  in gfx6_set_micro_tile_mode()
405 	tileb = MIN2(surf->u.legacy.tile_split, tileb);  in cik_get_macro_tile_index()
427 	surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;  in gfx6_surface_settings()
432 		surf->u.legacy.bankw = csio->pTileInfo->bankWidth;  in gfx6_surface_settings()
433 		surf->u.legacy.bankh = csio->pTileInfo->bankHeight;  in gfx6_surface_settings()
434 		surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;  in gfx6_surface_settings()
435 		surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;  in gfx6_surface_settings()
436 		surf->u.legacy.num_banks = csio->pTileInfo->banks;  in gfx6_surface_settings()
437 		surf->u.legacy.macro_tile_index = csio->macroModeIndex;  in gfx6_surface_settings()
439 		surf->u.legacy.macro_tile_index = 0;  in gfx6_surface_settings()
446 	    surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&  in gfx6_surface_settings()
629 	    surf->u.legacy.bankw && surf->u.legacy.bankh &&  in gfx6_compute_surface()
630 	    surf->u.legacy.mtilea && surf->u.legacy.tile_split) {  in gfx6_compute_surface()
635 		AddrTileInfoIn.banks = surf->u.legacy.num_banks;  in gfx6_compute_surface()
636 		AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;  in gfx6_compute_surface()
637 		AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;  in gfx6_compute_surface()
638 		AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;  in gfx6_compute_surface()
639 		AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;  in gfx6_compute_surface()
640 		AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */  in gfx6_compute_surface()
742 		AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;  in gfx6_compute_surface()
754 				if (surf->u.legacy.stencil_level[level].nblk_x !=  in gfx6_compute_surface()
755 				    surf->u.legacy.level[level].nblk_x)  in gfx6_compute_surface()
756 					surf->u.legacy.stencil_adjusted = true;  in gfx6_compute_surface()
758 				surf->u.legacy.level[level].nblk_x =  in gfx6_compute_surface()
759 					surf->u.legacy.stencil_level[level].nblk_x;  in gfx6_compute_surface()
772 					surf->u.legacy.stencil_tile_split =  in gfx6_compute_surface()
802 	surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;  in gfx6_compute_surface()