164 	ADDR_REGISTER_VALUE regValue = {0};  in amdgpu_addr_create()  local
172 	regValue.gbAddrConfig = amdinfo->gb_addr_cfg;  in amdgpu_addr_create()
181 		regValue.blockVarSizeLog2 = 0;  in amdgpu_addr_create()
183 		regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;  in amdgpu_addr_create()
184 		regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;  in amdgpu_addr_create()
186 		regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;  in amdgpu_addr_create()
187 		regValue.pTileConfig = amdinfo->gb_tile_mode;  in amdgpu_addr_create()
188 		regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);  in amdgpu_addr_create()
190 			regValue.pMacroTileConfig = NULL;  in amdgpu_addr_create()
191 			regValue.noOfMacroEntries = 0;  in amdgpu_addr_create()
193 			regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;  in amdgpu_addr_create()
194 			regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);  in amdgpu_addr_create()
207 	addrCreateInput.regValue = regValue;  in amdgpu_addr_create()