Lines Matching refs:radeon_emit
47 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
48 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2); in radeon_set_config_reg_seq()
54 radeon_emit(cs, value); in radeon_set_config_reg()
62 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
63 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_seq()
69 radeon_emit(cs, value); in radeon_set_context_reg()
79 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
80 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_context_reg_idx()
81 radeon_emit(cs, value); in radeon_set_context_reg_idx()
89 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0)); in radeon_set_sh_reg_seq()
90 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2); in radeon_set_sh_reg_seq()
96 radeon_emit(cs, value); in radeon_set_sh_reg()
104 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0)); in radeon_set_uconfig_reg_seq()
105 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); in radeon_set_uconfig_reg_seq()
111 radeon_emit(cs, value); in radeon_set_uconfig_reg()
120 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0)); in radeon_set_uconfig_reg_idx()
121 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_uconfig_reg_idx()
122 radeon_emit(cs, value); in radeon_set_uconfig_reg_idx()