Lines Matching refs:pipeline
53 struct radv_pipeline *pipeline, in radv_pipeline_destroy() argument
57 if (pipeline->shaders[i]) in radv_pipeline_destroy()
58 radv_shader_variant_destroy(device, pipeline->shaders[i]); in radv_pipeline_destroy()
60 if (pipeline->gs_copy_shader) in radv_pipeline_destroy()
61 radv_shader_variant_destroy(device, pipeline->gs_copy_shader); in radv_pipeline_destroy()
63 vk_free2(&device->alloc, allocator, pipeline); in radv_pipeline_destroy()
72 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline); in radv_DestroyPipeline()
77 radv_pipeline_destroy(device, pipeline, pAllocator); in radv_DestroyPipeline()
80 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline) in radv_dump_pipeline_stats() argument
85 if (!pipeline->shaders[i]) in radv_dump_pipeline_stats()
88 radv_shader_dump_stats(device, pipeline->shaders[i], i, stderr); in radv_dump_pipeline_stats()
105 struct radv_pipeline *pipeline) in radv_pipeline_scratch_init() argument
112 if (pipeline->shaders[i]) { in radv_pipeline_scratch_init()
116 pipeline->shaders[i]->config.scratch_bytes_per_wave); in radv_pipeline_scratch_init()
120 (256 / pipeline->shaders[i]->config.num_vgprs)); in radv_pipeline_scratch_init()
125 if (pipeline->shaders[MESA_SHADER_COMPUTE]) { in radv_pipeline_scratch_init()
126 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] * in radv_pipeline_scratch_init()
127 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] * in radv_pipeline_scratch_init()
128 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2]; in radv_pipeline_scratch_init()
140 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave; in radv_pipeline_scratch_init()
141 pipeline->max_waves = max_waves; in radv_pipeline_scratch_init()
420 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline, in radv_pipeline_compute_spi_color_formats() argument
429 struct radv_blend_state *blend = &pipeline->graphics.blend; in radv_pipeline_compute_spi_color_formats()
513 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline, in radv_pipeline_init_blend_state() argument
519 struct radv_blend_state *blend = &pipeline->graphics.blend; in radv_pipeline_init_blend_state()
657 if (pipeline->device->physical_device->has_rbplus) in radv_pipeline_init_blend_state()
665 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, in radv_pipeline_init_blend_state()
693 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline, in radv_pipeline_init_depth_stencil_state() argument
698 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds; in radv_pipeline_init_depth_stencil_state()
760 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline, in radv_pipeline_init_raster_state() argument
764 struct radv_raster_state *raster = &pipeline->graphics.raster; in radv_pipeline_init_raster_state()
814 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, in radv_pipeline_init_multisample_state() argument
818 struct radv_multisample_state *ms = &pipeline->graphics.ms; in radv_pipeline_init_multisample_state()
819 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes; in radv_pipeline_init_multisample_state()
830 …if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.fo… in radv_pipeline_init_multisample_state()
848 …ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_inf… in radv_pipeline_init_multisample_state()
865 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2); in radv_pipeline_init_multisample_state()
1032 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline, in radv_pipeline_init_dynamic_state() argument
1039 pipeline->dynamic_state = default_dynamic_state; in radv_pipeline_init_dynamic_state()
1048 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state; in radv_pipeline_init_dynamic_state()
1179 pipeline->graphics.pa_sc_cliprect_rule = mask; in radv_pipeline_init_dynamic_state()
1184 pipeline->graphics.pa_sc_cliprect_rule = 0xffff; in radv_pipeline_init_dynamic_state()
1186 pipeline->dynamic_state.mask = states; in radv_pipeline_init_dynamic_state()
1190 struct radv_pipeline *pipeline) in calculate_gfx9_gs_info() argument
1192 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info; in calculate_gfx9_gs_info()
1193 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ? in calculate_gfx9_gs_info()
1292 pipeline->graphics.gs.lds_size = align(esgs_lds_size, 128) / 128; in calculate_gfx9_gs_info()
1293 pipeline->graphics.gs.vgt_gs_onchip_cntl = in calculate_gfx9_gs_info()
1297 pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup = in calculate_gfx9_gs_info()
1299 pipeline->graphics.gs.vgt_esgs_ring_itemsize = esgs_itemsize; in calculate_gfx9_gs_info()
1304 calculate_gs_ring_sizes(struct radv_pipeline *pipeline) in calculate_gs_ring_sizes() argument
1306 struct radv_device *device = pipeline->device; in calculate_gs_ring_sizes()
1314 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info; in calculate_gs_ring_sizes()
1316 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) in calculate_gs_ring_sizes()
1317 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info; in calculate_gs_ring_sizes()
1319 es_info = radv_pipeline_has_tess(pipeline) ? in calculate_gs_ring_sizes()
1320 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info : in calculate_gs_ring_sizes()
1321 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info; in calculate_gs_ring_sizes()
1336 if (pipeline->device->physical_device->rad_info.chip_class <= VI) in calculate_gs_ring_sizes()
1337 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size); in calculate_gs_ring_sizes()
1339 pipeline->graphics.gs.vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4; in calculate_gs_ring_sizes()
1340 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size); in calculate_gs_ring_sizes()
1357 radv_get_vertex_shader(struct radv_pipeline *pipeline) in radv_get_vertex_shader() argument
1359 if (pipeline->shaders[MESA_SHADER_VERTEX]) in radv_get_vertex_shader()
1360 return pipeline->shaders[MESA_SHADER_VERTEX]; in radv_get_vertex_shader()
1361 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]) in radv_get_vertex_shader()
1362 return pipeline->shaders[MESA_SHADER_TESS_CTRL]; in radv_get_vertex_shader()
1363 return pipeline->shaders[MESA_SHADER_GEOMETRY]; in radv_get_vertex_shader()
1367 radv_get_tess_eval_shader(struct radv_pipeline *pipeline) in radv_get_tess_eval_shader() argument
1369 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) in radv_get_tess_eval_shader()
1370 return pipeline->shaders[MESA_SHADER_TESS_EVAL]; in radv_get_tess_eval_shader()
1371 return pipeline->shaders[MESA_SHADER_GEOMETRY]; in radv_get_tess_eval_shader()
1375 calculate_tess_state(struct radv_pipeline *pipeline, in calculate_tess_state() argument
1386 struct radv_tessellation_state *tess = &pipeline->graphics.tess; in calculate_tess_state()
1390 num_tcs_inputs = util_last_bit64(radv_get_vertex_shader(pipeline)->info.vs.outputs_written); in calculate_tess_state()
1392 …num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_writt… in calculate_tess_state()
1393 …num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VER… in calculate_tess_state()
1394 …num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_o… in calculate_tess_state()
1416 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768; in calculate_tess_state()
1421 (pipeline->device->tess_offchip_block_dw_size * 4) / in calculate_tess_state()
1430 if (pipeline->device->physical_device->rad_info.chip_class == SI) { in calculate_tess_state()
1440 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) { in calculate_tess_state()
1447 si_multiwave_lds_size_workaround(pipeline->device, &lds_size); in calculate_tess_state()
1466 struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline); in calculate_tess_state()
1512 if (pipeline->device->has_distributed_tess) { in calculate_tess_state()
1513 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI || in calculate_tess_state()
1514 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10) in calculate_tess_state()
1545 static struct ac_vs_output_info *get_vs_output_info(struct radv_pipeline *pipeline) in get_vs_output_info() argument
1547 if (radv_pipeline_has_gs(pipeline)) in get_vs_output_info()
1548 return &pipeline->gs_copy_shader->info.vs.outinfo; in get_vs_output_info()
1549 else if (radv_pipeline_has_tess(pipeline)) in get_vs_output_info()
1550 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo; in get_vs_output_info()
1552 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo; in get_vs_output_info()
1555 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline) in calculate_vgt_gs_mode() argument
1557 struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline); in calculate_vgt_gs_mode()
1559 pipeline->graphics.vgt_primitiveid_en = false; in calculate_vgt_gs_mode()
1560 pipeline->graphics.vgt_gs_mode = 0; in calculate_vgt_gs_mode()
1562 if (radv_pipeline_has_gs(pipeline)) { in calculate_vgt_gs_mode()
1564 pipeline->shaders[MESA_SHADER_GEOMETRY]; in calculate_vgt_gs_mode()
1566 pipeline->graphics.vgt_gs_mode = in calculate_vgt_gs_mode()
1568 pipeline->device->physical_device->rad_info.chip_class); in calculate_vgt_gs_mode()
1570 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A); in calculate_vgt_gs_mode()
1571 pipeline->graphics.vgt_primitiveid_en = true; in calculate_vgt_gs_mode()
1575 static void calculate_vs_outinfo(struct radv_pipeline *pipeline) in calculate_vs_outinfo() argument
1577 struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline); in calculate_vs_outinfo()
1587 pipeline->graphics.vs.pa_cl_vs_out_cntl = in calculate_vs_outinfo()
1598 pipeline->graphics.vs.spi_shader_pos_format = in calculate_vs_outinfo()
1610 …pipeline->graphics.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports)… in calculate_vs_outinfo()
1612 pipeline->graphics.vs.vgt_reuse_off = S_028AB4_REUSE_OFF(outinfo->writes_viewport_index); in calculate_vs_outinfo()
1633 static void calculate_ps_inputs(struct radv_pipeline *pipeline) in calculate_ps_inputs() argument
1636 struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline); in calculate_ps_inputs()
1638 ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; in calculate_ps_inputs()
1645 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true); in calculate_ps_inputs()
1653 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true); in calculate_ps_inputs()
1655 …pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, tr… in calculate_ps_inputs()
1662 pipeline->graphics.ps_input_cntl[ps_offset] = val; in calculate_ps_inputs()
1674 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20); in calculate_ps_inputs()
1681 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade); in calculate_ps_inputs()
1685 pipeline->graphics.ps_input_cntl_num = ps_offset; in calculate_ps_inputs()
1689 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders) in radv_link_shaders() argument
1725 pipeline->device->physical_device); in radv_link_shaders()
1731 pipeline->device->physical_device); in radv_link_shaders()
1740 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline, in radv_generate_graphics_pipeline_key() argument
1777 key.col_format = pipeline->graphics.blend.spi_shader_col_format; in radv_generate_graphics_pipeline_key()
1778 if (pipeline->device->physical_device->rad_info.chip_class < VI) in radv_generate_graphics_pipeline_key()
1857 void radv_create_shaders(struct radv_pipeline *pipeline, in radv_create_shaders() argument
1881 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device)); in radv_create_shaders()
1888 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY]; in radv_create_shaders()
1891 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) && in radv_create_shaders()
1892 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) { in radv_create_shaders()
1894 if (pipeline->shaders[i]) in radv_create_shaders()
1895 pipeline->active_stages |= mesa_to_vk_shader_stage(i); in radv_create_shaders()
1929 pipeline->active_stages |= mesa_to_vk_shader_stage(i); in radv_create_shaders()
1962 radv_link_shaders(pipeline, nir); in radv_create_shaders()
1972 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) { in radv_create_shaders()
1973 pipeline->shaders[MESA_SHADER_FRAGMENT] = in radv_create_shaders()
1975 pipeline->layout, keys + MESA_SHADER_FRAGMENT, in radv_create_shaders()
1981 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input; in radv_create_shaders()
1983 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input; in radv_create_shaders()
1987 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) { in radv_create_shaders()
1991 …pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_… in radv_create_shaders()
1992 pipeline->layout, in radv_create_shaders()
2001 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) { in radv_create_shaders()
2003 …pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_G… in radv_create_shaders()
2004 pipeline->layout, in radv_create_shaders()
2012 if(modules[i] && !pipeline->shaders[i]) { in radv_create_shaders()
2013 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1, in radv_create_shaders()
2014 pipeline->layout, in radv_create_shaders()
2023 if (!pipeline->gs_copy_shader) { in radv_create_shaders()
2024 pipeline->gs_copy_shader = radv_create_gs_copy_shader( in radv_create_shaders()
2030 if (pipeline->gs_copy_shader) { in radv_create_shaders()
2037 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader; in radv_create_shaders()
2048 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders, in radv_create_shaders()
2053 if (modules[i] && !pipeline->device->keep_shader_info) in radv_create_shaders()
2062 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline, in radv_pipeline_stage_to_user_data_0() argument
2065 bool has_gs = radv_pipeline_has_gs(pipeline); in radv_pipeline_stage_to_user_data_0()
2066 bool has_tess = radv_pipeline_has_tess(pipeline); in radv_pipeline_stage_to_user_data_0()
2108 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateIn… in radv_compute_bin_size() argument
2325 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends / in radv_compute_bin_size()
2326 pipeline->device->physical_device->rad_info.max_se); in radv_compute_bin_size()
2327 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se); in radv_compute_bin_size()
2329 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1); in radv_compute_bin_size()
2330 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa); in radv_compute_bin_size()
2332 unsigned cb_target_mask = pipeline->graphics.blend.cb_target_mask; in radv_compute_bin_size()
2377 radv_compute_binning_state(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCre… in radv_compute_binning_state() argument
2379 pipeline->graphics.bin.pa_sc_binner_cntl_0 = in radv_compute_binning_state()
2382 pipeline->graphics.bin.db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF); in radv_compute_binning_state()
2384 if (!pipeline->device->pbb_allowed) in radv_compute_binning_state()
2387 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo); in radv_compute_binning_state()
2395 switch (pipeline->device->physical_device->rad_info.family) { in radv_compute_binning_state()
2410 pipeline->graphics.bin.pa_sc_binner_cntl_0 = in radv_compute_binning_state()
2423 assert(!pipeline->device->dfsm_allowed); in radv_compute_binning_state()
2427 radv_pipeline_init(struct radv_pipeline *pipeline, in radv_pipeline_init() argument
2444 pipeline->device = device; in radv_pipeline_init()
2445 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout); in radv_pipeline_init()
2446 assert(pipeline->layout); in radv_pipeline_init()
2448 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo); in radv_pipeline_init()
2449 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra); in radv_pipeline_init()
2457 radv_create_shaders(pipeline, device, cache, in radv_pipeline_init()
2458 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, has_view_index), in radv_pipeline_init()
2461 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1); in radv_pipeline_init()
2462 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra); in radv_pipeline_init()
2463 radv_pipeline_init_raster_state(pipeline, pCreateInfo); in radv_pipeline_init()
2464 radv_pipeline_init_multisample_state(pipeline, pCreateInfo); in radv_pipeline_init()
2465 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology); in radv_pipeline_init()
2466 …pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyStat… in radv_pipeline_init()
2468 if (radv_pipeline_has_gs(pipeline)) { in radv_pipeline_init()
2469 …pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->inf… in radv_pipeline_init()
2470 …pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP; in radv_pipeline_init()
2472 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology); in radv_pipeline_init()
2475 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST; in radv_pipeline_init()
2476 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP; in radv_pipeline_init()
2477 pipeline->graphics.can_use_guardband = true; in radv_pipeline_init()
2479 …pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnabl… in radv_pipeline_init()
2481 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim]; in radv_pipeline_init()
2494 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; in radv_pipeline_init()
2495 if (!pipeline->graphics.blend.spi_shader_col_format) { in radv_pipeline_init()
2499 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R; in radv_pipeline_init()
2503 pipeline->graphics.db_shader_control = 0; in radv_pipeline_init()
2509 pipeline->graphics.db_shader_control = in radv_pipeline_init()
2519 if (pipeline->device->physical_device->has_rbplus) in radv_pipeline_init()
2520 pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1); in radv_pipeline_init()
2526 pipeline->graphics.shader_z_format = shader_z_format; in radv_pipeline_init()
2528 calculate_vgt_gs_mode(pipeline); in radv_pipeline_init()
2529 calculate_vs_outinfo(pipeline); in radv_pipeline_init()
2530 calculate_ps_inputs(pipeline); in radv_pipeline_init()
2533 if (pipeline->shaders[i]) { in radv_pipeline_init()
2534 …pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_set… in radv_pipeline_init()
2539 if (radv_pipeline_has_tess(pipeline)) { in radv_pipeline_init()
2543 if (radv_pipeline_has_gs(pipeline)) in radv_pipeline_init()
2550 } else if (radv_pipeline_has_gs(pipeline)) in radv_pipeline_init()
2558 pipeline->graphics.vgt_shader_stages_en = stages; in radv_pipeline_init()
2560 if (radv_pipeline_has_gs(pipeline)) { in radv_pipeline_init()
2561 calculate_gs_ring_sizes(pipeline); in radv_pipeline_init()
2563 calculate_gfx9_gs_info(pCreateInfo, pipeline); in radv_pipeline_init()
2566 if (radv_pipeline_has_tess(pipeline)) { in radv_pipeline_init()
2567 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) { in radv_pipeline_init()
2568 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints; in radv_pipeline_init()
2569 pipeline->graphics.prim_vertex_count.incr = 1; in radv_pipeline_init()
2571 calculate_tess_state(pipeline, pCreateInfo); in radv_pipeline_init()
2574 if (radv_pipeline_has_tess(pipeline)) in radv_pipeline_init()
2575 pipeline->graphics.primgroup_size = pipeline->graphics.tess.num_patches; in radv_pipeline_init()
2576 else if (radv_pipeline_has_gs(pipeline)) in radv_pipeline_init()
2577 pipeline->graphics.primgroup_size = 64; in radv_pipeline_init()
2579 pipeline->graphics.primgroup_size = 128; /* recommended without a GS */ in radv_pipeline_init()
2581 pipeline->graphics.partial_es_wave = false; in radv_pipeline_init()
2582 if (pipeline->device->has_distributed_tess) { in radv_pipeline_init()
2583 if (radv_pipeline_has_gs(pipeline)) { in radv_pipeline_init()
2585 pipeline->graphics.partial_es_wave = true; in radv_pipeline_init()
2589 if (SI_GS_PER_ES / pipeline->graphics.primgroup_size >= pipeline->device->gs_table_depth - 3) in radv_pipeline_init()
2590 pipeline->graphics.partial_es_wave = true; in radv_pipeline_init()
2592 pipeline->graphics.wd_switch_on_eop = false; in radv_pipeline_init()
2594 unsigned prim = pipeline->graphics.prim; in radv_pipeline_init()
2603 (pipeline->graphics.prim_restart_enable && in radv_pipeline_init()
2608 pipeline->graphics.wd_switch_on_eop = true; in radv_pipeline_init()
2611 pipeline->graphics.ia_switch_on_eoi = false; in radv_pipeline_init()
2612 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input) in radv_pipeline_init()
2613 pipeline->graphics.ia_switch_on_eoi = true; in radv_pipeline_init()
2614 if (radv_pipeline_has_gs(pipeline) && in radv_pipeline_init()
2615 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id) in radv_pipeline_init()
2616 pipeline->graphics.ia_switch_on_eoi = true; in radv_pipeline_init()
2617 if (radv_pipeline_has_tess(pipeline)) { in radv_pipeline_init()
2619 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id || in radv_pipeline_init()
2620 radv_get_tess_eval_shader(pipeline)->info.info.uses_prim_id) in radv_pipeline_init()
2621 pipeline->graphics.ia_switch_on_eoi = true; in radv_pipeline_init()
2624 pipeline->graphics.partial_vs_wave = false; in radv_pipeline_init()
2625 if (radv_pipeline_has_tess(pipeline)) { in radv_pipeline_init()
2630 radv_pipeline_has_gs(pipeline)) in radv_pipeline_init()
2631 pipeline->graphics.partial_vs_wave = true; in radv_pipeline_init()
2634 if (radv_pipeline_has_gs(pipeline)) { in radv_pipeline_init()
2640 pipeline->graphics.partial_vs_wave = true; in radv_pipeline_init()
2642 pipeline->graphics.partial_vs_wave = true; in radv_pipeline_init()
2647 pipeline->graphics.base_ia_multi_vgt_param = in radv_pipeline_init()
2648 S_028AA8_PRIMGROUP_SIZE(pipeline->graphics.primgroup_size - 1) | in radv_pipeline_init()
2656 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements; in radv_pipeline_init()
2687 pipeline->binding_stride[desc->binding] = desc->stride; in radv_pipeline_init()
2691 …pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device… in radv_pipeline_init()
2693 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, in radv_pipeline_init()
2696 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX]; in radv_pipeline_init()
2697 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4; in radv_pipeline_init()
2698 if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id) in radv_pipeline_init()
2699 pipeline->graphics.vtx_emit_num = 3; in radv_pipeline_init()
2701 pipeline->graphics.vtx_emit_num = 2; in radv_pipeline_init()
2704 pipeline->graphics.vtx_reuse_depth = 30; in radv_pipeline_init()
2705 if (radv_pipeline_has_tess(pipeline) && in radv_pipeline_init()
2706 radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) { in radv_pipeline_init()
2707 pipeline->graphics.vtx_reuse_depth = 14; in radv_pipeline_init()
2711 radv_dump_pipeline_stats(device, pipeline); in radv_pipeline_init()
2714 radv_compute_binning_state(pipeline, pCreateInfo); in radv_pipeline_init()
2716 result = radv_pipeline_scratch_init(device, pipeline); in radv_pipeline_init()
2731 struct radv_pipeline *pipeline; in radv_graphics_pipeline_create() local
2734 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8, in radv_graphics_pipeline_create()
2736 if (pipeline == NULL) in radv_graphics_pipeline_create()
2739 result = radv_pipeline_init(pipeline, device, cache, in radv_graphics_pipeline_create()
2742 radv_pipeline_destroy(device, pipeline, pAllocator); in radv_graphics_pipeline_create()
2746 *pPipeline = radv_pipeline_to_handle(pipeline); in radv_graphics_pipeline_create()
2787 struct radv_pipeline *pipeline; in radv_compute_pipeline_create() local
2790 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8, in radv_compute_pipeline_create()
2792 if (pipeline == NULL) in radv_compute_pipeline_create()
2795 pipeline->device = device; in radv_compute_pipeline_create()
2796 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout); in radv_compute_pipeline_create()
2797 assert(pipeline->layout); in radv_compute_pipeline_create()
2800 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages); in radv_compute_pipeline_create()
2802 …pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHA… in radv_compute_pipeline_create()
2803 …pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indir… in radv_compute_pipeline_create()
2804 result = radv_pipeline_scratch_init(device, pipeline); in radv_compute_pipeline_create()
2806 radv_pipeline_destroy(device, pipeline, pAllocator); in radv_compute_pipeline_create()
2810 *pPipeline = radv_pipeline_to_handle(pipeline); in radv_compute_pipeline_create()
2813 radv_dump_pipeline_stats(device, pipeline); in radv_compute_pipeline_create()