342 	radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));  in si_emit_config()
347 		radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));  in si_emit_config()
843 		radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, predicated));  in si_cs_emit_write_event_eop()
859 			radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));  in si_cs_emit_write_event_eop()
867 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));  in si_cs_emit_write_event_eop()
882 	radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, predicated));  in si_emit_wait_fence()
900 		radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, predicated) |  in si_emit_acquire_mem()
910 		radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, predicated));  in si_emit_acquire_mem()
964 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));  in si_cs_emit_cache_flush()
969 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));  in si_cs_emit_cache_flush()
974 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));  in si_cs_emit_cache_flush()
977 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));  in si_cs_emit_cache_flush()
982 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));  in si_cs_emit_cache_flush()
1046 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));  in si_cs_emit_cache_flush()
1059 		radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));  in si_cs_emit_cache_flush()
1150 		radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));  in si_emit_set_predication_state()
1155 		radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));  in si_emit_set_predication_state()
1233 		radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));  in si_emit_cp_dma()
1243 		radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));  in si_emit_cp_dma()
1257 		radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));  in si_emit_cp_dma()