179                 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_a], n);  in process_mux_deps()
182                 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_b], n);  in process_mux_deps()
282         struct v3d_qpu_instr *inst = &qinst->qpu;  in calculate_deps()
508         const struct v3d_qpu_instr *inst = &qinst->qpu;  in reads_too_soon_after_write()
548         const struct v3d_qpu_instr *inst = &qinst->qpu;  in writes_too_soon_after_write()
741                 if (prev_inst->inst->qpu.sig.thrsw)  in choose_instruction_to_schedule()
746                 const struct v3d_qpu_instr *inst = &n->inst->qpu;  in choose_instruction_to_schedule()
809                                             &prev_inst->inst->qpu, inst)) {  in choose_instruction_to_schedule()
894                 v3d_qpu_dump(devinfo, &n->inst->qpu);  in dump_state()
903                         v3d_qpu_dump(devinfo, &child->inst->qpu);  in dump_state()
950         const struct v3d_qpu_instr *before_inst = &before->inst->qpu;  in instruction_latency()
951         const struct v3d_qpu_instr *after_inst = &after->inst->qpu;  in instruction_latency()
1038         update_scoreboard_for_chosen(scoreboard, &inst->qpu);  in insert_scheduled_instruction()
1063         const struct v3d_qpu_instr *inst = &qinst->qpu;  in qpu_instruction_valid_in_thrend_slot()
1125                     qinst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&  in valid_thrsw_sequence()
1126                     (v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.add.waddr) ||  in valid_thrsw_sequence()
1127                      v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.mul.waddr))) {  in valid_thrsw_sequence()
1131                 if (slot > 0 && qinst->qpu.sig.ldvary)  in valid_thrsw_sequence()
1164         assert(inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU);  in emit_thrsw()
1165         assert(inst->qpu.alu.add.op == V3D_QPU_A_NOP);  in emit_thrsw()
1166         assert(inst->qpu.alu.mul.op == V3D_QPU_M_NOP);  in emit_thrsw()
1172                 struct v3d_qpu_sig sig = prev_inst->qpu.sig;  in emit_thrsw()
1191                 merge_inst->qpu.sig.thrsw = true;  in emit_thrsw()
1212                 second_inst->qpu.sig.thrsw = true;  in emit_thrsw()
1260                 struct v3d_qpu_instr *inst = &qinst->qpu;  in schedule_instructions()
1288                                                      inst, &merge->inst->qpu);  in schedule_instructions()
1297                                         v3d_qpu_dump(devinfo, &merge->inst->qpu);  in schedule_instructions()
1435                 assert(branch->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH);  in qpu_set_branch_targets()
1445                 branch->qpu.branch.offset =  in qpu_set_branch_targets()
1496                                 v3d_qpu_dump(devinfo, &qinst->qpu);  in v3d_qpu_schedule_instructions()
1521         thrsw->qpu.sig.thrsw = true;  in v3d_qpu_schedule_instructions()