36 check_uniforms(const struct etna_inst *inst)  in check_uniforms()  argument
43       const struct etna_inst_src *src = &inst->src[i];  in check_uniforms()
62 etna_assemble(uint32_t *out, const struct etna_inst *inst)  in etna_assemble()  argument
65    if (inst->imm && inst->src[2].use)  in etna_assemble()
68    if (!check_uniforms(inst))  in etna_assemble()
71    assert(!(inst->opcode&~0x7f));  in etna_assemble()
73    out[0] = VIV_ISA_WORD_0_OPCODE(inst->opcode & 0x3f) |  in etna_assemble()
74             VIV_ISA_WORD_0_COND(inst->cond) |  in etna_assemble()
75             COND(inst->sat, VIV_ISA_WORD_0_SAT) |  in etna_assemble()
76             COND(inst->dst.use, VIV_ISA_WORD_0_DST_USE) |  in etna_assemble()
77             VIV_ISA_WORD_0_DST_AMODE(inst->dst.amode) |  in etna_assemble()
78             VIV_ISA_WORD_0_DST_REG(inst->dst.reg) |  in etna_assemble()
79             VIV_ISA_WORD_0_DST_COMPS(inst->dst.comps) |  in etna_assemble()
80             VIV_ISA_WORD_0_TEX_ID(inst->tex.id);  in etna_assemble()
81    out[1] = VIV_ISA_WORD_1_TEX_AMODE(inst->tex.amode) |  in etna_assemble()
82             VIV_ISA_WORD_1_TEX_SWIZ(inst->tex.swiz) |  in etna_assemble()
83             COND(inst->src[0].use, VIV_ISA_WORD_1_SRC0_USE) |  in etna_assemble()
84             VIV_ISA_WORD_1_SRC0_REG(inst->src[0].reg) |  in etna_assemble()
85             COND(inst->type & 0x4, VIV_ISA_WORD_1_TYPE_BIT2) |  in etna_assemble()
86             VIV_ISA_WORD_1_SRC0_SWIZ(inst->src[0].swiz) |  in etna_assemble()
87             COND(inst->src[0].neg, VIV_ISA_WORD_1_SRC0_NEG) |  in etna_assemble()
88             COND(inst->src[0].abs, VIV_ISA_WORD_1_SRC0_ABS);  in etna_assemble()
89    out[2] = VIV_ISA_WORD_2_SRC0_AMODE(inst->src[0].amode) |  in etna_assemble()
90             VIV_ISA_WORD_2_SRC0_RGROUP(inst->src[0].rgroup) |  in etna_assemble()
91             COND(inst->src[1].use, VIV_ISA_WORD_2_SRC1_USE) |  in etna_assemble()
92             VIV_ISA_WORD_2_SRC1_REG(inst->src[1].reg) |  in etna_assemble()
93             COND(inst->opcode & 0x40, VIV_ISA_WORD_2_OPCODE_BIT6) |  in etna_assemble()
94             VIV_ISA_WORD_2_SRC1_SWIZ(inst->src[1].swiz) |  in etna_assemble()
95             COND(inst->src[1].neg, VIV_ISA_WORD_2_SRC1_NEG) |  in etna_assemble()
96             COND(inst->src[1].abs, VIV_ISA_WORD_2_SRC1_ABS) |  in etna_assemble()
97             VIV_ISA_WORD_2_SRC1_AMODE(inst->src[1].amode) |  in etna_assemble()
98             VIV_ISA_WORD_2_TYPE_BIT01(inst->type & 0x3);  in etna_assemble()
99    out[3] = VIV_ISA_WORD_3_SRC1_RGROUP(inst->src[1].rgroup) |  in etna_assemble()
100             COND(inst->src[2].use, VIV_ISA_WORD_3_SRC2_USE) |  in etna_assemble()
101             VIV_ISA_WORD_3_SRC2_REG(inst->src[2].reg) |  in etna_assemble()
102             VIV_ISA_WORD_3_SRC2_SWIZ(inst->src[2].swiz) |  in etna_assemble()
103             COND(inst->src[2].neg, VIV_ISA_WORD_3_SRC2_NEG) |  in etna_assemble()
104             COND(inst->src[2].abs, VIV_ISA_WORD_3_SRC2_ABS) |  in etna_assemble()
105             VIV_ISA_WORD_3_SRC2_AMODE(inst->src[2].amode) |  in etna_assemble()
106             VIV_ISA_WORD_3_SRC2_RGROUP(inst->src[2].rgroup);  in etna_assemble()
107    out[3] |= VIV_ISA_WORD_3_SRC2_IMM(inst->imm);  in etna_assemble()