811 	struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;  in r600_init_color_surface()  local
822 	if (rtex->db_compatible && !r600_can_sample_zs(rtex, false)) {  in r600_init_color_surface()
824 		rtex = rtex->flushed_depth_texture;  in r600_init_color_surface()
825 		assert(rtex);  in r600_init_color_surface()
828 	offset = rtex->surface.u.legacy.level[level].offset;  in r600_init_color_surface()
832 	pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1;  in r600_init_color_surface()
833 …slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) …  in r600_init_color_surface()
838 	switch (rtex->surface.u.legacy.level[level].mode) {  in r600_init_color_surface()
877 		do_endian_swap = !rtex->db_compatible;  in r600_init_color_surface()
956 	r600_resource_reference(&surf->cb_buffer_cmask, &rtex->resource);  in r600_init_color_surface()
957 	r600_resource_reference(&surf->cb_buffer_fmask, &rtex->resource);  in r600_init_color_surface()
959 	if (rtex->cmask.size) {  in r600_init_color_surface()
960 		surf->cb_color_cmask = rtex->cmask.offset >> 8;  in r600_init_color_surface()
961 		surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);  in r600_init_color_surface()
963 		if (rtex->fmask.size) {  in r600_init_color_surface()
965 			surf->cb_color_fmask = rtex->fmask.offset >> 8;  in r600_init_color_surface()
966 			surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);  in r600_init_color_surface()
980 		r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);  in r600_init_color_surface()
981 		r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);  in r600_init_color_surface()
1041 	struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;  in r600_init_depth_surface()  local
1045 	offset = rtex->surface.u.legacy.level[level].offset;  in r600_init_depth_surface()
1046 	pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1;  in r600_init_depth_surface()
1047 …slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) …  in r600_init_depth_surface()
1051 	switch (rtex->surface.u.legacy.level[level].mode) {  in r600_init_depth_surface()
1070 	surf->db_prefetch_limit = (rtex->surface.u.legacy.level[level].nblk_y / 8) - 1;  in r600_init_depth_surface()
1072 	if (r600_htile_enabled(rtex, level)) {  in r600_init_depth_surface()
1073 		surf->db_htile_data_base = rtex->htile_offset >> 8;  in r600_init_depth_surface()
1089 	struct r600_texture *rtex;  in r600_set_framebuffer_state()  local
1128 		rtex = (struct r600_texture*)surf->base.texture;  in r600_set_framebuffer_state()
1143 		if (rtex->fmask.size) {  in r600_set_framebuffer_state()
1548 		struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;  in r600_emit_db_state()  local
1551 		radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));  in r600_emit_db_state()
1554 		reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,  in r600_emit_db_state()