Lines Matching refs:fmask
554 rtex->fmask = new_tex->fmask; in r600_reallocate_texture_inplace()
568 assert(!rtex->fmask.size); in r600_reallocate_texture_inplace()
602 assert(rtex->fmask.size == 0); in si_query_opaque_metadata()
841 struct radeon_surf fmask = {}; in si_texture_get_fmask_info() local
869 RADEON_SURF_MODE_2D, &fmask)) { in si_texture_get_fmask_info()
874 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D); in si_texture_get_fmask_info()
876 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64; in si_texture_get_fmask_info()
880 out->tile_mode_index = fmask.u.legacy.tiling_index[0]; in si_texture_get_fmask_info()
881 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x; in si_texture_get_fmask_info()
882 out->bank_height = fmask.u.legacy.bankh; in si_texture_get_fmask_info()
883 out->tile_swizzle = fmask.tile_swizzle; in si_texture_get_fmask_info()
884 out->alignment = MAX2(256, fmask.surf_alignment); in si_texture_get_fmask_info()
885 out->size = fmask.surf_size; in si_texture_get_fmask_info()
892 rtex->resource.b.b.nr_samples, &rtex->fmask); in r600_texture_allocate_fmask()
894 rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment); in r600_texture_allocate_fmask()
895 rtex->size = rtex->fmask.offset + rtex->fmask.size; in r600_texture_allocate_fmask()
1070 if (rtex->fmask.size) { in si_print_texture_info()
1073 rtex->fmask.offset, in si_print_texture_info()
1076 rtex->surface.u.gfx9.fmask.swizzle_mode, in si_print_texture_info()
1077 rtex->surface.u.gfx9.fmask.epitch); in si_print_texture_info()
1125 if (rtex->fmask.size) in si_print_texture_info()
1128 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment, in si_print_texture_info()
1129 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height, in si_print_texture_info()
1130 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index); in si_print_texture_info()
1272 if (!rtex->fmask.size || !rtex->cmask.size) { in r600_texture_create_object()