Lines Matching refs:rtex
40 struct r600_texture *rtex);
182 struct r600_texture *rtex, unsigned level, in r600_texture_get_offset() argument
188 *stride = rtex->surface.u.gfx9.surf_pitch * rtex->surface.bpe; in r600_texture_get_offset()
189 *layer_stride = rtex->surface.u.gfx9.surf_slice_size; in r600_texture_get_offset()
196 return box->z * rtex->surface.u.gfx9.surf_slice_size + in r600_texture_get_offset()
197 rtex->surface.u.gfx9.offset[level] + in r600_texture_get_offset()
198 (box->y / rtex->surface.blk_h * in r600_texture_get_offset()
199 rtex->surface.u.gfx9.surf_pitch + in r600_texture_get_offset()
200 box->x / rtex->surface.blk_w) * rtex->surface.bpe; in r600_texture_get_offset()
202 *stride = rtex->surface.u.legacy.level[level].nblk_x * in r600_texture_get_offset()
203 rtex->surface.bpe; in r600_texture_get_offset()
204 assert((uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 <= UINT_MAX); in r600_texture_get_offset()
205 *layer_stride = (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4; in r600_texture_get_offset()
208 return rtex->surface.u.legacy.level[level].offset; in r600_texture_get_offset()
212 return rtex->surface.u.legacy.level[level].offset + in r600_texture_get_offset()
213 box->z * (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 + in r600_texture_get_offset()
214 (box->y / rtex->surface.blk_h * in r600_texture_get_offset()
215 rtex->surface.u.legacy.level[level].nblk_x + in r600_texture_get_offset()
216 box->x / rtex->surface.blk_w) * rtex->surface.bpe; in r600_texture_get_offset()
325 struct r600_texture *rtex, in r600_texture_init_metadata() argument
328 struct radeon_surf *surface = &rtex->surface; in r600_texture_init_metadata()
386 struct r600_texture *rtex) in r600_eliminate_fast_color_clear() argument
394 ctx->flush_resource(ctx, &rtex->resource.b.b); in r600_eliminate_fast_color_clear()
402 struct r600_texture *rtex) in r600_texture_discard_cmask() argument
404 if (!rtex->cmask.size) in r600_texture_discard_cmask()
407 assert(rtex->resource.b.b.nr_samples <= 1); in r600_texture_discard_cmask()
410 memset(&rtex->cmask, 0, sizeof(rtex->cmask)); in r600_texture_discard_cmask()
411 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8; in r600_texture_discard_cmask()
412 rtex->dirty_level_mask = 0; in r600_texture_discard_cmask()
414 rtex->cb_color_info &= ~S_028C70_FAST_CLEAR(1); in r600_texture_discard_cmask()
416 if (rtex->cmask_buffer != &rtex->resource) in r600_texture_discard_cmask()
417 r600_resource_reference(&rtex->cmask_buffer, NULL); in r600_texture_discard_cmask()
424 static bool r600_can_disable_dcc(struct r600_texture *rtex) in r600_can_disable_dcc() argument
427 return rtex->dcc_offset && in r600_can_disable_dcc()
428 (!rtex->resource.b.is_shared || in r600_can_disable_dcc()
429 !(rtex->resource.external_usage & PIPE_HANDLE_USAGE_WRITE)); in r600_can_disable_dcc()
433 struct r600_texture *rtex) in r600_texture_discard_dcc() argument
435 if (!r600_can_disable_dcc(rtex)) in r600_texture_discard_dcc()
438 assert(rtex->dcc_separate_buffer == NULL); in r600_texture_discard_dcc()
441 rtex->dcc_offset = 0; in r600_texture_discard_dcc()
470 struct r600_texture *rtex) in si_texture_disable_dcc() argument
474 if (!r600_can_disable_dcc(rtex)) in si_texture_disable_dcc()
481 rctx->decompress_dcc(&rctx->b, rtex); in si_texture_disable_dcc()
487 return r600_texture_discard_dcc(sscreen, rtex); in si_texture_disable_dcc()
491 struct r600_texture *rtex, in r600_reallocate_texture_inplace() argument
497 struct pipe_resource templ = rtex->resource.b.b; in r600_reallocate_texture_inplace()
502 if (rtex->resource.b.is_shared) in r600_reallocate_texture_inplace()
506 if (rtex->surface.is_linear) in r600_reallocate_texture_inplace()
529 &rtex->resource.b.b, i, &box); in r600_reallocate_texture_inplace()
534 r600_texture_discard_cmask(rctx->screen, rtex); in r600_reallocate_texture_inplace()
535 r600_texture_discard_dcc(rctx->screen, rtex); in r600_reallocate_texture_inplace()
539 rtex->resource.b.b.bind = templ.bind; in r600_reallocate_texture_inplace()
540 pb_reference(&rtex->resource.buf, new_tex->resource.buf); in r600_reallocate_texture_inplace()
541 rtex->resource.gpu_address = new_tex->resource.gpu_address; in r600_reallocate_texture_inplace()
542 rtex->resource.vram_usage = new_tex->resource.vram_usage; in r600_reallocate_texture_inplace()
543 rtex->resource.gart_usage = new_tex->resource.gart_usage; in r600_reallocate_texture_inplace()
544 rtex->resource.bo_size = new_tex->resource.bo_size; in r600_reallocate_texture_inplace()
545 rtex->resource.bo_alignment = new_tex->resource.bo_alignment; in r600_reallocate_texture_inplace()
546 rtex->resource.domains = new_tex->resource.domains; in r600_reallocate_texture_inplace()
547 rtex->resource.flags = new_tex->resource.flags; in r600_reallocate_texture_inplace()
548 rtex->size = new_tex->size; in r600_reallocate_texture_inplace()
549 rtex->db_render_format = new_tex->db_render_format; in r600_reallocate_texture_inplace()
550 rtex->db_compatible = new_tex->db_compatible; in r600_reallocate_texture_inplace()
551 rtex->can_sample_z = new_tex->can_sample_z; in r600_reallocate_texture_inplace()
552 rtex->can_sample_s = new_tex->can_sample_s; in r600_reallocate_texture_inplace()
553 rtex->surface = new_tex->surface; in r600_reallocate_texture_inplace()
554 rtex->fmask = new_tex->fmask; in r600_reallocate_texture_inplace()
555 rtex->cmask = new_tex->cmask; in r600_reallocate_texture_inplace()
556 rtex->cb_color_info = new_tex->cb_color_info; in r600_reallocate_texture_inplace()
557 rtex->last_msaa_resolve_target_micro_mode = new_tex->last_msaa_resolve_target_micro_mode; in r600_reallocate_texture_inplace()
558 rtex->htile_offset = new_tex->htile_offset; in r600_reallocate_texture_inplace()
559 rtex->tc_compatible_htile = new_tex->tc_compatible_htile; in r600_reallocate_texture_inplace()
560 rtex->depth_cleared = new_tex->depth_cleared; in r600_reallocate_texture_inplace()
561 rtex->stencil_cleared = new_tex->stencil_cleared; in r600_reallocate_texture_inplace()
562 rtex->dcc_gather_statistics = new_tex->dcc_gather_statistics; in r600_reallocate_texture_inplace()
563 rtex->framebuffers_bound = new_tex->framebuffers_bound; in r600_reallocate_texture_inplace()
566 assert(!rtex->htile_offset); in r600_reallocate_texture_inplace()
567 assert(!rtex->cmask.size); in r600_reallocate_texture_inplace()
568 assert(!rtex->fmask.size); in r600_reallocate_texture_inplace()
569 assert(!rtex->dcc_offset); in r600_reallocate_texture_inplace()
570 assert(!rtex->is_depth); in r600_reallocate_texture_inplace()
584 struct r600_texture *rtex, in si_query_opaque_metadata() argument
587 struct pipe_resource *res = &rtex->resource.b.b; in si_query_opaque_metadata()
601 assert(rtex->dcc_separate_buffer == NULL); in si_query_opaque_metadata()
602 assert(rtex->fmask.size == 0); in si_query_opaque_metadata()
619 si_make_texture_descriptor(sscreen, rtex, true, in si_query_opaque_metadata()
626 si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0], in si_query_opaque_metadata()
627 0, 0, rtex->surface.blk_w, false, desc); in si_query_opaque_metadata()
632 desc[7] = rtex->dcc_offset >> 8; in si_query_opaque_metadata()
641 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8; in si_query_opaque_metadata()
648 struct r600_texture *rtex, in si_apply_opaque_metadata() argument
663 rtex->dcc_offset = (uint64_t)desc[7] << 8; in si_apply_opaque_metadata()
670 rtex->dcc_offset = 0; in si_apply_opaque_metadata()
682 struct r600_texture *rtex = (struct r600_texture*)resource; in r600_texture_get_handle() local
695 if (resource->nr_samples > 1 || rtex->is_depth) in r600_texture_get_handle()
700 rtex->surface.tile_swizzle || in r600_texture_get_handle()
701 (rtex->resource.flags & RADEON_FLAG_NO_INTERPROCESS_SHARING && in r600_texture_get_handle()
704 r600_reallocate_texture_inplace(rctx, rtex, in r600_texture_get_handle()
710 assert(rtex->surface.tile_swizzle == 0); in r600_texture_get_handle()
717 if (usage & PIPE_HANDLE_USAGE_WRITE && rtex->dcc_offset) { in r600_texture_get_handle()
718 if (si_texture_disable_dcc(rctx, rtex)) { in r600_texture_get_handle()
726 (rtex->cmask.size || rtex->dcc_offset)) { in r600_texture_get_handle()
728 r600_eliminate_fast_color_clear(rctx, rtex); in r600_texture_get_handle()
735 if (rtex->cmask.size) in r600_texture_get_handle()
736 r600_texture_discard_cmask(sscreen, rtex); in r600_texture_get_handle()
741 r600_texture_init_metadata(sscreen, rtex, &metadata); in r600_texture_get_handle()
742 si_query_opaque_metadata(sscreen, rtex, &metadata); in r600_texture_get_handle()
748 offset = rtex->surface.u.gfx9.surf_offset; in r600_texture_get_handle()
749 stride = rtex->surface.u.gfx9.surf_pitch * in r600_texture_get_handle()
750 rtex->surface.bpe; in r600_texture_get_handle()
751 slice_size = rtex->surface.u.gfx9.surf_slice_size; in r600_texture_get_handle()
753 offset = rtex->surface.u.legacy.level[0].offset; in r600_texture_get_handle()
754 stride = rtex->surface.u.legacy.level[0].nblk_x * in r600_texture_get_handle()
755 rtex->surface.bpe; in r600_texture_get_handle()
756 slice_size = (uint64_t)rtex->surface.u.legacy.level[0].slice_size_dw * 4; in r600_texture_get_handle()
763 rtex->resource.flags & RADEON_FLAG_NO_INTERPROCESS_SHARING) { in r600_texture_get_handle()
817 struct r600_texture *rtex = (struct r600_texture*)ptex; in r600_texture_destroy() local
818 struct r600_resource *resource = &rtex->resource; in r600_texture_destroy()
820 r600_texture_reference(&rtex->flushed_depth_texture, NULL); in r600_texture_destroy()
822 if (rtex->cmask_buffer != &rtex->resource) { in r600_texture_destroy()
823 r600_resource_reference(&rtex->cmask_buffer, NULL); in r600_texture_destroy()
826 r600_resource_reference(&rtex->dcc_separate_buffer, NULL); in r600_texture_destroy()
827 r600_resource_reference(&rtex->last_dcc_separate_buffer, NULL); in r600_texture_destroy()
828 FREE(rtex); in r600_texture_destroy()
835 struct r600_texture *rtex, in si_texture_get_fmask_info() argument
840 struct pipe_resource templ = rtex->resource.b.b; in si_texture_get_fmask_info()
847 out->alignment = rtex->surface.u.gfx9.fmask_alignment; in si_texture_get_fmask_info()
848 out->size = rtex->surface.u.gfx9.fmask_size; in si_texture_get_fmask_info()
853 flags = rtex->surface.flags | RADEON_SURF_FMASK; in si_texture_get_fmask_info()
889 struct r600_texture *rtex) in r600_texture_allocate_fmask() argument
891 si_texture_get_fmask_info(sscreen, rtex, in r600_texture_allocate_fmask()
892 rtex->resource.b.b.nr_samples, &rtex->fmask); in r600_texture_allocate_fmask()
894 rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment); in r600_texture_allocate_fmask()
895 rtex->size = rtex->fmask.offset + rtex->fmask.size; in r600_texture_allocate_fmask()
899 struct r600_texture *rtex, in si_texture_get_cmask_info() argument
907 out->alignment = rtex->surface.u.gfx9.cmask_alignment; in si_texture_get_cmask_info()
908 out->size = rtex->surface.u.gfx9.cmask_size; in si_texture_get_cmask_info()
936 unsigned width = align(rtex->resource.b.b.width0, cl_width*8); in si_texture_get_cmask_info()
937 unsigned height = align(rtex->resource.b.b.height0, cl_height*8); in si_texture_get_cmask_info()
948 out->size = util_num_layers(&rtex->resource.b.b, 0) * in si_texture_get_cmask_info()
953 struct r600_texture *rtex) in r600_texture_allocate_cmask() argument
955 si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask); in r600_texture_allocate_cmask()
957 rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment); in r600_texture_allocate_cmask()
958 rtex->size = rtex->cmask.offset + rtex->cmask.size; in r600_texture_allocate_cmask()
960 rtex->cb_color_info |= S_028C70_FAST_CLEAR(1); in r600_texture_allocate_cmask()
964 struct r600_texture *rtex) in r600_texture_get_htile_size() argument
972 rtex->surface.htile_size = 0; in r600_texture_get_htile_size()
976 rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D && in r600_texture_get_htile_size()
1016 width = align(rtex->resource.b.b.width0, cl_width * 8); in r600_texture_get_htile_size()
1017 height = align(rtex->resource.b.b.height0, cl_height * 8); in r600_texture_get_htile_size()
1025 rtex->surface.htile_alignment = base_align; in r600_texture_get_htile_size()
1026 rtex->surface.htile_size = in r600_texture_get_htile_size()
1027 util_num_layers(&rtex->resource.b.b, 0) * in r600_texture_get_htile_size()
1032 struct r600_texture *rtex) in r600_texture_allocate_htile() argument
1034 if (sscreen->info.chip_class <= VI && !rtex->tc_compatible_htile) in r600_texture_allocate_htile()
1035 r600_texture_get_htile_size(sscreen, rtex); in r600_texture_allocate_htile()
1037 if (!rtex->surface.htile_size) in r600_texture_allocate_htile()
1040 rtex->htile_offset = align(rtex->size, rtex->surface.htile_alignment); in r600_texture_allocate_htile()
1041 rtex->size = rtex->htile_offset + rtex->surface.htile_size; in r600_texture_allocate_htile()
1045 struct r600_texture *rtex, struct u_log_context *log) in si_print_texture_info() argument
1053 rtex->resource.b.b.width0, rtex->resource.b.b.height0, in si_print_texture_info()
1054 rtex->resource.b.b.depth0, rtex->surface.blk_w, in si_print_texture_info()
1055 rtex->surface.blk_h, in si_print_texture_info()
1056 rtex->resource.b.b.array_size, rtex->resource.b.b.last_level, in si_print_texture_info()
1057 rtex->surface.bpe, rtex->resource.b.b.nr_samples, in si_print_texture_info()
1058 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format)); in si_print_texture_info()
1063 rtex->surface.surf_size, in si_print_texture_info()
1064 rtex->surface.u.gfx9.surf_slice_size, in si_print_texture_info()
1065 rtex->surface.surf_alignment, in si_print_texture_info()
1066 rtex->surface.u.gfx9.surf.swizzle_mode, in si_print_texture_info()
1067 rtex->surface.u.gfx9.surf.epitch, in si_print_texture_info()
1068 rtex->surface.u.gfx9.surf_pitch); in si_print_texture_info()
1070 if (rtex->fmask.size) { in si_print_texture_info()
1073 rtex->fmask.offset, in si_print_texture_info()
1074 rtex->surface.u.gfx9.fmask_size, in si_print_texture_info()
1075 rtex->surface.u.gfx9.fmask_alignment, in si_print_texture_info()
1076 rtex->surface.u.gfx9.fmask.swizzle_mode, in si_print_texture_info()
1077 rtex->surface.u.gfx9.fmask.epitch); in si_print_texture_info()
1080 if (rtex->cmask.size) { in si_print_texture_info()
1083 rtex->cmask.offset, in si_print_texture_info()
1084 rtex->surface.u.gfx9.cmask_size, in si_print_texture_info()
1085 rtex->surface.u.gfx9.cmask_alignment, in si_print_texture_info()
1086 rtex->surface.u.gfx9.cmask.rb_aligned, in si_print_texture_info()
1087 rtex->surface.u.gfx9.cmask.pipe_aligned); in si_print_texture_info()
1090 if (rtex->htile_offset) { in si_print_texture_info()
1093 rtex->htile_offset, in si_print_texture_info()
1094 rtex->surface.htile_size, in si_print_texture_info()
1095 rtex->surface.htile_alignment, in si_print_texture_info()
1096 rtex->surface.u.gfx9.htile.rb_aligned, in si_print_texture_info()
1097 rtex->surface.u.gfx9.htile.pipe_aligned); in si_print_texture_info()
1100 if (rtex->dcc_offset) { in si_print_texture_info()
1103 rtex->dcc_offset, rtex->surface.dcc_size, in si_print_texture_info()
1104 rtex->surface.dcc_alignment, in si_print_texture_info()
1105 rtex->surface.u.gfx9.dcc_pitch_max, in si_print_texture_info()
1106 rtex->surface.num_dcc_levels); in si_print_texture_info()
1109 if (rtex->surface.u.gfx9.stencil_offset) { in si_print_texture_info()
1111 rtex->surface.u.gfx9.stencil_offset, in si_print_texture_info()
1112 rtex->surface.u.gfx9.stencil.swizzle_mode, in si_print_texture_info()
1113 rtex->surface.u.gfx9.stencil.epitch); in si_print_texture_info()
1120 rtex->surface.surf_size, rtex->surface.surf_alignment, rtex->surface.u.legacy.bankw, in si_print_texture_info()
1121 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea, in si_print_texture_info()
1122 rtex->surface.u.legacy.tile_split, rtex->surface.u.legacy.pipe_config, in si_print_texture_info()
1123 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0); in si_print_texture_info()
1125 if (rtex->fmask.size) in si_print_texture_info()
1128 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment, in si_print_texture_info()
1129 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height, in si_print_texture_info()
1130 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index); in si_print_texture_info()
1132 if (rtex->cmask.size) in si_print_texture_info()
1135 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment, in si_print_texture_info()
1136 rtex->cmask.slice_tile_max); in si_print_texture_info()
1138 if (rtex->htile_offset) in si_print_texture_info()
1141 rtex->htile_offset, rtex->surface.htile_size, in si_print_texture_info()
1142 rtex->surface.htile_alignment, in si_print_texture_info()
1143 rtex->tc_compatible_htile); in si_print_texture_info()
1145 if (rtex->dcc_offset) { in si_print_texture_info()
1147 rtex->dcc_offset, rtex->surface.dcc_size, in si_print_texture_info()
1148 rtex->surface.dcc_alignment); in si_print_texture_info()
1149 for (i = 0; i <= rtex->resource.b.b.last_level; i++) in si_print_texture_info()
1152 i, i < rtex->surface.num_dcc_levels, in si_print_texture_info()
1153 rtex->surface.u.legacy.level[i].dcc_offset, in si_print_texture_info()
1154 rtex->surface.u.legacy.level[i].dcc_fast_clear_size); in si_print_texture_info()
1157 for (i = 0; i <= rtex->resource.b.b.last_level; i++) in si_print_texture_info()
1161 i, rtex->surface.u.legacy.level[i].offset, in si_print_texture_info()
1162 (uint64_t)rtex->surface.u.legacy.level[i].slice_size_dw * 4, in si_print_texture_info()
1163 u_minify(rtex->resource.b.b.width0, i), in si_print_texture_info()
1164 u_minify(rtex->resource.b.b.height0, i), in si_print_texture_info()
1165 u_minify(rtex->resource.b.b.depth0, i), in si_print_texture_info()
1166 rtex->surface.u.legacy.level[i].nblk_x, in si_print_texture_info()
1167 rtex->surface.u.legacy.level[i].nblk_y, in si_print_texture_info()
1168 rtex->surface.u.legacy.level[i].mode, in si_print_texture_info()
1169 rtex->surface.u.legacy.tiling_index[i]); in si_print_texture_info()
1171 if (rtex->surface.has_stencil) { in si_print_texture_info()
1173 rtex->surface.u.legacy.stencil_tile_split); in si_print_texture_info()
1174 for (i = 0; i <= rtex->resource.b.b.last_level; i++) { in si_print_texture_info()
1179 i, rtex->surface.u.legacy.stencil_level[i].offset, in si_print_texture_info()
1180 (uint64_t)rtex->surface.u.legacy.stencil_level[i].slice_size_dw * 4, in si_print_texture_info()
1181 u_minify(rtex->resource.b.b.width0, i), in si_print_texture_info()
1182 u_minify(rtex->resource.b.b.height0, i), in si_print_texture_info()
1183 u_minify(rtex->resource.b.b.depth0, i), in si_print_texture_info()
1184 rtex->surface.u.legacy.stencil_level[i].nblk_x, in si_print_texture_info()
1185 rtex->surface.u.legacy.stencil_level[i].nblk_y, in si_print_texture_info()
1186 rtex->surface.u.legacy.stencil_level[i].mode, in si_print_texture_info()
1187 rtex->surface.u.legacy.stencil_tiling_index[i]); in si_print_texture_info()
1199 struct r600_texture *rtex; in r600_texture_create_object() local
1203 rtex = CALLOC_STRUCT(r600_texture); in r600_texture_create_object()
1204 if (!rtex) in r600_texture_create_object()
1207 resource = &rtex->resource; in r600_texture_create_object()
1215 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format)); in r600_texture_create_object()
1217 rtex->surface = *surface; in r600_texture_create_object()
1218 rtex->size = rtex->surface.surf_size; in r600_texture_create_object()
1220 rtex->tc_compatible_htile = rtex->surface.htile_size != 0 && in r600_texture_create_object()
1221 (rtex->surface.flags & in r600_texture_create_object()
1227 if (rtex->tc_compatible_htile) { in r600_texture_create_object()
1230 rtex->db_render_format = base->format; in r600_texture_create_object()
1232 rtex->db_render_format = PIPE_FORMAT_Z32_FLOAT; in r600_texture_create_object()
1233 rtex->upgraded_depth = base->format != PIPE_FORMAT_Z32_FLOAT && in r600_texture_create_object()
1237 rtex->db_render_format = base->format; in r600_texture_create_object()
1241 rtex->last_msaa_resolve_target_micro_mode = rtex->surface.micro_tile_mode; in r600_texture_create_object()
1247 rtex->ps_draw_ratio = 0; in r600_texture_create_object()
1249 if (rtex->is_depth) { in r600_texture_create_object()
1251 rtex->can_sample_z = true; in r600_texture_create_object()
1252 rtex->can_sample_s = true; in r600_texture_create_object()
1254 rtex->can_sample_z = !rtex->surface.u.legacy.depth_adjusted; in r600_texture_create_object()
1255 rtex->can_sample_s = !rtex->surface.u.legacy.stencil_adjusted; in r600_texture_create_object()
1260 rtex->db_compatible = true; in r600_texture_create_object()
1263 r600_texture_allocate_htile(sscreen, rtex); in r600_texture_create_object()
1268 r600_texture_allocate_fmask(sscreen, rtex); in r600_texture_create_object()
1269 r600_texture_allocate_cmask(sscreen, rtex); in r600_texture_create_object()
1270 rtex->cmask_buffer = &rtex->resource; in r600_texture_create_object()
1272 if (!rtex->fmask.size || !rtex->cmask.size) { in r600_texture_create_object()
1273 FREE(rtex); in r600_texture_create_object()
1282 if (rtex->surface.dcc_size && in r600_texture_create_object()
1284 !(rtex->surface.flags & RADEON_SURF_SCANOUT)) { in r600_texture_create_object()
1286 rtex->dcc_offset = align64(rtex->size, rtex->surface.dcc_alignment); in r600_texture_create_object()
1287 rtex->size = rtex->dcc_offset + rtex->surface.dcc_size; in r600_texture_create_object()
1293 si_init_resource_fields(sscreen, resource, rtex->size, in r600_texture_create_object()
1294 rtex->surface.surf_alignment); in r600_texture_create_object()
1297 FREE(rtex); in r600_texture_create_object()
1312 if (rtex->cmask.size) { in r600_texture_create_object()
1314 si_screen_clear_buffer(sscreen, &rtex->cmask_buffer->b.b, in r600_texture_create_object()
1315 rtex->cmask.offset, rtex->cmask.size, in r600_texture_create_object()
1318 if (rtex->htile_offset) { in r600_texture_create_object()
1321 if (sscreen->info.chip_class >= GFX9 || rtex->tc_compatible_htile) in r600_texture_create_object()
1324 si_screen_clear_buffer(sscreen, &rtex->resource.b.b, in r600_texture_create_object()
1325 rtex->htile_offset, in r600_texture_create_object()
1326 rtex->surface.htile_size, in r600_texture_create_object()
1331 if (!buf && rtex->dcc_offset) { in r600_texture_create_object()
1332 si_screen_clear_buffer(sscreen, &rtex->resource.b.b, in r600_texture_create_object()
1333 rtex->dcc_offset, in r600_texture_create_object()
1334 rtex->surface.dcc_size, in r600_texture_create_object()
1339 rtex->cmask.base_address_reg = in r600_texture_create_object()
1340 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8; in r600_texture_create_object()
1344 rtex->resource.gpu_address, in r600_texture_create_object()
1345 rtex->resource.gpu_address + rtex->resource.buf->size, in r600_texture_create_object()
1354 si_print_texture_info(sscreen, rtex, &log); in r600_texture_create_object()
1360 return rtex; in r600_texture_create_object()
1472 struct r600_texture *rtex; in r600_texture_from_handle() local
1494 rtex = r600_texture_create_object(screen, templ, buf, &surface); in r600_texture_from_handle()
1495 if (!rtex) in r600_texture_from_handle()
1498 rtex->resource.b.is_shared = true; in r600_texture_from_handle()
1499 rtex->resource.external_usage = usage; in r600_texture_from_handle()
1501 si_apply_opaque_metadata(sscreen, rtex, &metadata); in r600_texture_from_handle()
1503 assert(rtex->surface.tile_swizzle == 0); in r600_texture_from_handle()
1504 return &rtex->resource.b.b; in r600_texture_from_handle()
1511 struct r600_texture *rtex = (struct r600_texture*)texture; in si_init_flushed_depth_texture() local
1514 staging : &rtex->flushed_depth_texture; in si_init_flushed_depth_texture()
1518 if (rtex->flushed_depth_texture) in si_init_flushed_depth_texture()
1521 if (!rtex->can_sample_z && rtex->can_sample_s) { in si_init_flushed_depth_texture()
1542 } else if (!rtex->can_sample_s && rtex->can_sample_z) { in si_init_flushed_depth_texture()
1603 struct r600_texture *rtex, in r600_can_invalidate_texture() argument
1607 return !rtex->resource.b.is_shared && in r600_can_invalidate_texture()
1609 rtex->resource.b.b.last_level == 0 && in r600_can_invalidate_texture()
1610 util_texrange_covers_whole_level(&rtex->resource.b.b, 0, in r600_can_invalidate_texture()
1617 struct r600_texture *rtex) in r600_texture_invalidate_storage() argument
1622 assert(!rtex->is_depth); in r600_texture_invalidate_storage()
1623 assert(rtex->surface.is_linear); in r600_texture_invalidate_storage()
1626 si_alloc_resource(sscreen, &rtex->resource); in r600_texture_invalidate_storage()
1629 rtex->cmask.base_address_reg = in r600_texture_invalidate_storage()
1630 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8; in r600_texture_invalidate_storage()
1634 rctx->num_alloc_tex_transfer_bytes += rtex->size; in r600_texture_invalidate_storage()
1645 struct r600_texture *rtex = (struct r600_texture*)texture; in r600_texture_transfer_map() local
1656 if (!rtex->is_depth) { in r600_texture_transfer_map()
1664 p_atomic_inc_return(&rtex->num_level0_transfers) == 10) { in r600_texture_transfer_map()
1666 r600_can_invalidate_texture(rctx->screen, rtex, in r600_texture_transfer_map()
1669 r600_reallocate_texture_inplace(rctx, rtex, in r600_texture_transfer_map()
1683 if (!rtex->surface.is_linear) in r600_texture_transfer_map()
1687 rtex->resource.domains & RADEON_DOMAIN_VRAM || in r600_texture_transfer_map()
1688 rtex->resource.flags & RADEON_FLAG_GTT_WC; in r600_texture_transfer_map()
1690 else if (si_rings_is_buffer_referenced(rctx, rtex->resource.buf, in r600_texture_transfer_map()
1692 !rctx->ws->buffer_wait(rtex->resource.buf, 0, in r600_texture_transfer_map()
1695 if (r600_can_invalidate_texture(rctx->screen, rtex, in r600_texture_transfer_map()
1697 r600_texture_invalidate_storage(rctx, rtex); in r600_texture_transfer_map()
1711 if (rtex->is_depth) { in r600_texture_transfer_map()
1714 if (rtex->resource.b.b.nr_samples > 1) { in r600_texture_transfer_map()
1762 rctx->blit_decompress_depth(ctx, rtex, staging_depth, in r600_texture_transfer_map()
1806 offset = r600_texture_get_offset(rctx->screen, rtex, level, box, in r600_texture_transfer_map()
1809 buf = &rtex->resource; in r600_texture_transfer_map()
1828 struct r600_texture *rtex = (struct r600_texture*)texture; in r600_texture_transfer_unmap() local
1831 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) { in r600_texture_transfer_unmap()
1965 struct r600_texture *rtex = (struct r600_texture *)tex; in vi_dcc_formats_are_incompatible() local
1967 return vi_dcc_enabled(rtex, level) && in vi_dcc_formats_are_incompatible()
1978 struct r600_texture *rtex = (struct r600_texture *)tex; in vi_disable_dcc_if_incompatible_format() local
1982 rctx->decompress_dcc(&rctx->b, rtex); in vi_disable_dcc_if_incompatible_format()
2408 struct r600_texture *rtex; in r600_texture_from_memobj() local
2454 rtex = r600_texture_create_object(screen, templ, memobj->buf, &surface); in r600_texture_from_memobj()
2455 if (!rtex) in r600_texture_from_memobj()
2463 rtex->resource.b.is_shared = true; in r600_texture_from_memobj()
2464 rtex->resource.external_usage = PIPE_HANDLE_USAGE_READ_WRITE; in r600_texture_from_memobj()
2466 si_apply_opaque_metadata(sscreen, rtex, &metadata); in r600_texture_from_memobj()
2468 return &rtex->resource.b.b; in r600_texture_from_memobj()