Lines Matching refs:rtex
37 struct r600_texture *rtex) in si_alloc_separate_cmask() argument
39 if (rtex->cmask_buffer) in si_alloc_separate_cmask()
42 assert(rtex->cmask.size == 0); in si_alloc_separate_cmask()
44 si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask); in si_alloc_separate_cmask()
45 if (!rtex->cmask.size) in si_alloc_separate_cmask()
48 rtex->cmask_buffer = (struct r600_resource *) in si_alloc_separate_cmask()
52 rtex->cmask.size, in si_alloc_separate_cmask()
53 rtex->cmask.alignment); in si_alloc_separate_cmask()
54 if (rtex->cmask_buffer == NULL) { in si_alloc_separate_cmask()
55 rtex->cmask.size = 0; in si_alloc_separate_cmask()
60 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8; in si_alloc_separate_cmask()
62 rtex->cb_color_info |= S_028C70_FAST_CLEAR(1); in si_alloc_separate_cmask()
67 static void si_set_clear_color(struct r600_texture *rtex, in si_set_clear_color() argument
75 if (rtex->surface.bpe == 16) { in si_set_clear_color()
92 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t)); in si_set_clear_color()
194 struct r600_texture *rtex, in vi_dcc_clear_level() argument
200 assert(vi_dcc_enabled(rtex, level)); in vi_dcc_clear_level()
202 if (rtex->dcc_separate_buffer) { in vi_dcc_clear_level()
203 dcc_buffer = &rtex->dcc_separate_buffer->b.b; in vi_dcc_clear_level()
206 dcc_buffer = &rtex->resource.b.b; in vi_dcc_clear_level()
207 dcc_offset = rtex->dcc_offset; in vi_dcc_clear_level()
212 assert(rtex->resource.b.b.last_level == 0); in vi_dcc_clear_level()
214 assert(rtex->resource.b.b.nr_samples <= 1); in vi_dcc_clear_level()
215 clear_size = rtex->surface.dcc_size; in vi_dcc_clear_level()
217 unsigned num_layers = util_num_layers(&rtex->resource.b.b, level); in vi_dcc_clear_level()
220 assert(rtex->surface.u.legacy.level[level].dcc_fast_clear_size); in vi_dcc_clear_level()
225 assert(rtex->resource.b.b.nr_samples <= 1 || num_layers == 1); in vi_dcc_clear_level()
227 dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset; in vi_dcc_clear_level()
228 clear_size = rtex->surface.u.legacy.level[level].dcc_fast_clear_size * in vi_dcc_clear_level()
241 struct r600_texture *rtex) in si_set_optimal_micro_tile_mode() argument
243 if (rtex->resource.b.is_shared || in si_set_optimal_micro_tile_mode()
244 rtex->resource.b.b.nr_samples <= 1 || in si_set_optimal_micro_tile_mode()
245 rtex->surface.micro_tile_mode == rtex->last_msaa_resolve_target_micro_mode) in si_set_optimal_micro_tile_mode()
249 rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D); in si_set_optimal_micro_tile_mode()
250 assert(rtex->resource.b.b.last_level == 0); in si_set_optimal_micro_tile_mode()
254 assert(rtex->surface.u.gfx9.surf.swizzle_mode >= 4); in si_set_optimal_micro_tile_mode()
264 assert(rtex->surface.u.gfx9.surf.swizzle_mode % 4 != 0); in si_set_optimal_micro_tile_mode()
266 switch (rtex->last_msaa_resolve_target_micro_mode) { in si_set_optimal_micro_tile_mode()
268 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
269 rtex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */ in si_set_optimal_micro_tile_mode()
272 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
273 rtex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */ in si_set_optimal_micro_tile_mode()
276 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
277 rtex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */ in si_set_optimal_micro_tile_mode()
288 switch (rtex->last_msaa_resolve_target_micro_mode) { in si_set_optimal_micro_tile_mode()
290 rtex->surface.u.legacy.tiling_index[0] = 10; in si_set_optimal_micro_tile_mode()
293 rtex->surface.u.legacy.tiling_index[0] = 14; in si_set_optimal_micro_tile_mode()
296 rtex->surface.u.legacy.tiling_index[0] = 28; in si_set_optimal_micro_tile_mode()
303 switch (rtex->last_msaa_resolve_target_micro_mode) { in si_set_optimal_micro_tile_mode()
305 switch (rtex->surface.bpe) { in si_set_optimal_micro_tile_mode()
307 rtex->surface.u.legacy.tiling_index[0] = 10; in si_set_optimal_micro_tile_mode()
310 rtex->surface.u.legacy.tiling_index[0] = 11; in si_set_optimal_micro_tile_mode()
313 rtex->surface.u.legacy.tiling_index[0] = 12; in si_set_optimal_micro_tile_mode()
318 switch (rtex->surface.bpe) { in si_set_optimal_micro_tile_mode()
320 rtex->surface.u.legacy.tiling_index[0] = 14; in si_set_optimal_micro_tile_mode()
323 rtex->surface.u.legacy.tiling_index[0] = 15; in si_set_optimal_micro_tile_mode()
326 rtex->surface.u.legacy.tiling_index[0] = 16; in si_set_optimal_micro_tile_mode()
329 rtex->surface.u.legacy.tiling_index[0] = 17; in si_set_optimal_micro_tile_mode()
339 rtex->surface.micro_tile_mode = rtex->last_msaa_resolve_target_micro_mode; in si_set_optimal_micro_tile_mode()
669 struct r600_texture *rtex = (struct r600_texture*)tex; in si_clear_texture() local
683 if (rtex->is_depth) { in si_clear_texture()
692 if (rtex->surface.has_stencil) { in si_clear_texture()