Lines Matching refs:rtex
1917 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex, in si_tex_dim() argument
1920 unsigned res_target = rtex->resource.b.b.target; in si_tex_dim()
1934 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) { in si_tex_dim()
2349 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; in si_initialize_color_surface() local
2435 if (rtex->resource.b.b.nr_samples > 1) { in si_initialize_color_surface()
2436 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples); in si_initialize_color_surface()
2441 if (rtex->fmask.size) { in si_initialize_color_surface()
2443 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height); in si_initialize_color_surface()
2463 if (rtex->resource.b.b.nr_samples > 1) { in si_initialize_color_surface()
2464 if (rtex->surface.bpe == 1) in si_initialize_color_surface()
2466 else if (rtex->surface.bpe == 2) in si_initialize_color_surface()
2476 if (!rtex->fmask.size && sctx->b.chip_class == SI) { in si_initialize_color_surface()
2477 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh); in si_initialize_color_surface()
2485 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0); in si_initialize_color_surface()
2489 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type); in si_initialize_color_surface()
2492 S_028C68_MAX_MIP(rtex->resource.b.b.last_level); in si_initialize_color_surface()
2500 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth); in si_initialize_color_surface()
2508 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; in si_init_depth_surface() local
2513 format = si_translate_dbformat(rtex->db_render_format); in si_init_depth_surface()
2514 stencil_format = rtex->surface.has_stencil ? in si_init_depth_surface()
2519 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format); in si_init_depth_surface()
2527 assert(rtex->surface.u.gfx9.surf_offset == 0); in si_init_depth_surface()
2528 surf->db_depth_base = rtex->resource.gpu_address >> 8; in si_init_depth_surface()
2529 surf->db_stencil_base = (rtex->resource.gpu_address + in si_init_depth_surface()
2530 rtex->surface.u.gfx9.stencil_offset) >> 8; in si_init_depth_surface()
2532 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) | in si_init_depth_surface()
2533 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) | in si_init_depth_surface()
2534 S_028038_MAXMIP(rtex->resource.b.b.last_level); in si_init_depth_surface()
2536 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode); in si_init_depth_surface()
2537 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch); in si_init_depth_surface()
2538 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch); in si_init_depth_surface()
2540 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) | in si_init_depth_surface()
2541 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1); in si_init_depth_surface()
2543 if (si_htile_enabled(rtex, level)) { in si_init_depth_surface()
2547 if (rtex->tc_compatible_htile) { in si_init_depth_surface()
2550 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM && in si_init_depth_surface()
2551 rtex->resource.b.b.nr_samples > 1) in si_init_depth_surface()
2559 if (rtex->surface.has_stencil) { in si_init_depth_surface()
2563 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1); in si_init_depth_surface()
2569 surf->db_htile_data_base = (rtex->resource.gpu_address + in si_init_depth_surface()
2570 rtex->htile_offset) >> 8; in si_init_depth_surface()
2572 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) | in si_init_depth_surface()
2573 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned); in si_init_depth_surface()
2577 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level]; in si_init_depth_surface()
2581 surf->db_depth_base = (rtex->resource.gpu_address + in si_init_depth_surface()
2582 rtex->surface.u.legacy.level[level].offset) >> 8; in si_init_depth_surface()
2583 surf->db_stencil_base = (rtex->resource.gpu_address + in si_init_depth_surface()
2584 rtex->surface.u.legacy.stencil_level[level].offset) >> 8; in si_init_depth_surface()
2587 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)); in si_init_depth_surface()
2589 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile); in si_init_depth_surface()
2593 unsigned index = rtex->surface.u.legacy.tiling_index[level]; in si_init_depth_surface()
2594 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level]; in si_init_depth_surface()
2595 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index; in si_init_depth_surface()
2610 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false); in si_init_depth_surface()
2612 tile_mode_index = si_tile_mode_index(rtex, level, true); in si_init_depth_surface()
2621 if (si_htile_enabled(rtex, level)) { in si_init_depth_surface()
2625 if (rtex->surface.has_stencil) { in si_init_depth_surface()
2637 if (rtex->resource.b.b.nr_samples <= 1) in si_init_depth_surface()
2639 } else if (!rtex->tc_compatible_htile) { in si_init_depth_surface()
2647 surf->db_htile_data_base = (rtex->resource.gpu_address + in si_init_depth_surface()
2648 rtex->htile_offset) >> 8; in si_init_depth_surface()
2651 if (rtex->tc_compatible_htile) { in si_init_depth_surface()
2654 if (rtex->resource.b.b.nr_samples <= 1) in si_init_depth_surface()
2656 else if (rtex->resource.b.b.nr_samples <= 4) in si_init_depth_surface()
2677 struct r600_texture *rtex = (struct r600_texture *)surf->texture; in si_update_fb_dirtiness_after_rendering() local
2679 rtex->dirty_level_mask |= 1 << surf->u.tex.level; in si_update_fb_dirtiness_after_rendering()
2681 if (rtex->surface.has_stencil) in si_update_fb_dirtiness_after_rendering()
2682 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level; in si_update_fb_dirtiness_after_rendering()
2689 struct r600_texture *rtex = (struct r600_texture*)surf->texture; in si_update_fb_dirtiness_after_rendering() local
2691 if (rtex->fmask.size) in si_update_fb_dirtiness_after_rendering()
2692 rtex->dirty_level_mask |= 1 << surf->u.tex.level; in si_update_fb_dirtiness_after_rendering()
2693 if (rtex->dcc_gather_statistics) in si_update_fb_dirtiness_after_rendering()
2694 rtex->separate_dcc_dirty = true; in si_update_fb_dirtiness_after_rendering()
2702 struct r600_texture *rtex; in si_dec_framebuffer_counters() local
2707 rtex = (struct r600_texture*)surf->base.texture; in si_dec_framebuffer_counters()
2709 p_atomic_dec(&rtex->framebuffers_bound); in si_dec_framebuffer_counters()
2719 struct r600_texture *rtex; in si_set_framebuffer_state() local
2736 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture; in si_set_framebuffer_state()
2737 if (rtex->dcc_gather_statistics) in si_set_framebuffer_state()
2738 vi_separate_dcc_stop_query(ctx, rtex); in si_set_framebuffer_state()
2747 rtex = (struct r600_texture*)surf->base.texture; in si_set_framebuffer_state()
2762 if (vi_dcc_enabled(rtex, surf->base.u.tex.level)) in si_set_framebuffer_state()
2763 if (!si_texture_disable_dcc(&sctx->b, rtex)) in si_set_framebuffer_state()
2764 sctx->b.decompress_dcc(ctx, rtex); in si_set_framebuffer_state()
2842 rtex = (struct r600_texture*)surf->base.texture; in si_set_framebuffer_state()
2863 if (rtex->fmask.size) { in si_set_framebuffer_state()
2867 if (rtex->surface.is_linear) in si_set_framebuffer_state()
2870 if (vi_dcc_enabled(rtex, surf->base.u.tex.level)) in si_set_framebuffer_state()
2875 p_atomic_inc(&rtex->framebuffers_bound); in si_set_framebuffer_state()
2877 if (rtex->dcc_gather_statistics) { in si_set_framebuffer_state()
2880 vi_separate_dcc_start_query(ctx, rtex); in si_set_framebuffer_state()
3131 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture; in si_emit_framebuffer_state() local
3134 &rtex->resource, RADEON_USAGE_READWRITE, in si_emit_framebuffer_state()
3147 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0)); in si_emit_framebuffer_state()
3167 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0)); in si_emit_framebuffer_state()
3178 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */ in si_emit_framebuffer_state()
3179 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */ in si_emit_framebuffer_state()