3130 		struct r600_surface *zb = (struct r600_surface*)state->zsbuf;  in si_emit_framebuffer_state()  local
3131 		struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;  in si_emit_framebuffer_state()
3135 				      zb->base.texture->nr_samples > 1 ?  in si_emit_framebuffer_state()
3141 			radeon_emit(cs, zb->db_htile_data_base);	/* DB_HTILE_DATA_BASE */  in si_emit_framebuffer_state()
3142 			radeon_emit(cs, zb->db_htile_data_base >> 32);	/* DB_HTILE_DATA_BASE_HI */  in si_emit_framebuffer_state()
3143 			radeon_emit(cs, zb->db_depth_size);		/* DB_DEPTH_SIZE */  in si_emit_framebuffer_state()
3146 			radeon_emit(cs, zb->db_z_info |			/* DB_Z_INFO */  in si_emit_framebuffer_state()
3148 			radeon_emit(cs, zb->db_stencil_info);		/* DB_STENCIL_INFO */  in si_emit_framebuffer_state()
3149 			radeon_emit(cs, zb->db_depth_base);		/* DB_Z_READ_BASE */  in si_emit_framebuffer_state()
3150 			radeon_emit(cs, zb->db_depth_base >> 32);	/* DB_Z_READ_BASE_HI */  in si_emit_framebuffer_state()
3151 			radeon_emit(cs, zb->db_stencil_base);		/* DB_STENCIL_READ_BASE */  in si_emit_framebuffer_state()
3152 			radeon_emit(cs, zb->db_stencil_base >> 32);	/* DB_STENCIL_READ_BASE_HI */  in si_emit_framebuffer_state()
3153 			radeon_emit(cs, zb->db_depth_base);		/* DB_Z_WRITE_BASE */  in si_emit_framebuffer_state()
3154 			radeon_emit(cs, zb->db_depth_base >> 32);	/* DB_Z_WRITE_BASE_HI */  in si_emit_framebuffer_state()
3155 			radeon_emit(cs, zb->db_stencil_base);		/* DB_STENCIL_WRITE_BASE */  in si_emit_framebuffer_state()
3156 			radeon_emit(cs, zb->db_stencil_base >> 32);	/* DB_STENCIL_WRITE_BASE_HI */  in si_emit_framebuffer_state()
3159 			radeon_emit(cs, zb->db_z_info2);	/* DB_Z_INFO2 */  in si_emit_framebuffer_state()
3160 			radeon_emit(cs, zb->db_stencil_info2);	/* DB_STENCIL_INFO2 */  in si_emit_framebuffer_state()
3162 			radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);  in si_emit_framebuffer_state()
3165 			radeon_emit(cs, zb->db_depth_info);	/* DB_DEPTH_INFO */  in si_emit_framebuffer_state()
3166 			radeon_emit(cs, zb->db_z_info |		/* DB_Z_INFO */  in si_emit_framebuffer_state()
3168 			radeon_emit(cs, zb->db_stencil_info);	/* DB_STENCIL_INFO */  in si_emit_framebuffer_state()
3169 			radeon_emit(cs, zb->db_depth_base);	/* DB_Z_READ_BASE */  in si_emit_framebuffer_state()
3170 			radeon_emit(cs, zb->db_stencil_base);	/* DB_STENCIL_READ_BASE */  in si_emit_framebuffer_state()
3171 			radeon_emit(cs, zb->db_depth_base);	/* DB_Z_WRITE_BASE */  in si_emit_framebuffer_state()
3172 			radeon_emit(cs, zb->db_stencil_base);	/* DB_STENCIL_WRITE_BASE */  in si_emit_framebuffer_state()
3173 			radeon_emit(cs, zb->db_depth_size);	/* DB_DEPTH_SIZE */  in si_emit_framebuffer_state()
3174 			radeon_emit(cs, zb->db_depth_slice);	/* DB_DEPTH_SLICE */  in si_emit_framebuffer_state()
3181 		radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);  in si_emit_framebuffer_state()
3182 		radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);  in si_emit_framebuffer_state()