Lines Matching refs:inst
316 vec4_visitor::implied_mrf_writes(vec4_instruction *inst) in implied_mrf_writes() argument
318 if (inst->mlen == 0 || inst->is_send_from_grf()) in implied_mrf_writes()
321 switch (inst->opcode) { in implied_mrf_writes()
365 return inst->header_size; in implied_mrf_writes()
393 foreach_inst_in_block_safe(vec4_instruction, inst, block) { in opt_vector_float()
402 if (inst->opcode == BRW_OPCODE_MOV && in opt_vector_float()
403 inst->src[0].file == IMM && in opt_vector_float()
404 inst->predicate == BRW_PREDICATE_NONE && in opt_vector_float()
405 inst->dst.writemask != WRITEMASK_XYZW && in opt_vector_float()
406 type_sz(inst->src[0].type) < 8 && in opt_vector_float()
407 (inst->src[0].type == inst->dst.type || inst->src[0].d == 0)) { in opt_vector_float()
409 vf = brw_float_to_vf(inst->src[0].d); in opt_vector_float()
413 vf = brw_float_to_vf(inst->src[0].f); in opt_vector_float()
424 if (last_reg != inst->dst.nr || in opt_vector_float()
425 last_offset != inst->dst.offset || in opt_vector_float()
426 last_reg_file != inst->dst.file || in opt_vector_float()
435 inst->insert_before(block, mov); in opt_vector_float()
456 if ((inst->dst.writemask & WRITEMASK_X) != 0) in opt_vector_float()
458 if ((inst->dst.writemask & WRITEMASK_Y) != 0) in opt_vector_float()
460 if ((inst->dst.writemask & WRITEMASK_Z) != 0) in opt_vector_float()
462 if ((inst->dst.writemask & WRITEMASK_W) != 0) in opt_vector_float()
465 writemask |= inst->dst.writemask; in opt_vector_float()
466 imm_inst[inst_count++] = inst; in opt_vector_float()
468 last_reg = inst->dst.nr; in opt_vector_float()
469 last_offset = inst->dst.offset; in opt_vector_float()
470 last_reg_file = inst->dst.file; in opt_vector_float()
501 foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { in opt_reduce_swizzle()
502 if (inst->dst.file == BAD_FILE || in opt_reduce_swizzle()
503 inst->dst.file == ARF || in opt_reduce_swizzle()
504 inst->dst.file == FIXED_GRF || in opt_reduce_swizzle()
505 inst->is_send_from_grf()) in opt_reduce_swizzle()
511 switch (inst->opcode) { in opt_reduce_swizzle()
538 swizzle = brw_swizzle_for_mask(inst->dst.writemask); in opt_reduce_swizzle()
544 if (inst->src[i].file != VGRF && in opt_reduce_swizzle()
545 inst->src[i].file != ATTR && in opt_reduce_swizzle()
546 inst->src[i].file != UNIFORM) in opt_reduce_swizzle()
550 brw_compose_swizzle(swizzle, inst->src[i].swizzle); in opt_reduce_swizzle()
551 if (inst->src[i].swizzle != new_swizzle) { in opt_reduce_swizzle()
552 inst->src[i].swizzle = new_swizzle; in opt_reduce_swizzle()
574 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in split_uniform_registers()
576 if (inst->src[i].file != UNIFORM) in split_uniform_registers()
579 assert(!inst->src[i].reladdr); in split_uniform_registers()
581 inst->src[i].nr += inst->src[i].offset / 16; in split_uniform_registers()
582 inst->src[i].offset %= 16; in split_uniform_registers()
632 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in pack_uniform_registers()
634 switch (inst->opcode) { in pack_uniform_registers()
647 readmask = inst->dst.writemask; in pack_uniform_registers()
652 if (inst->src[i].file != UNIFORM) in pack_uniform_registers()
655 assert(type_sz(inst->src[i].type) % 4 == 0); in pack_uniform_registers()
656 int channel_size = type_sz(inst->src[i].type) / 4; in pack_uniform_registers()
658 int reg = inst->src[i].nr; in pack_uniform_registers()
663 unsigned channel = BRW_GET_SWZ(inst->src[i].swizzle, c) + 1; in pack_uniform_registers()
677 if (inst->opcode == SHADER_OPCODE_MOV_INDIRECT && in pack_uniform_registers()
678 inst->src[0].file == UNIFORM) { in pack_uniform_registers()
679 assert(inst->src[2].file == BRW_IMMEDIATE_VALUE); in pack_uniform_registers()
680 assert(inst->src[0].subnr == 0); in pack_uniform_registers()
682 unsigned bytes_read = inst->src[2].ud; in pack_uniform_registers()
690 int reg = inst->src[0].nr; in pack_uniform_registers()
691 int channel_size = type_sz(inst->src[0].type) / 4; in pack_uniform_registers()
757 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in pack_uniform_registers()
759 int src = inst->src[i].nr; in pack_uniform_registers()
761 if (inst->src[i].file != UNIFORM) in pack_uniform_registers()
765 inst->src[i].nr = new_loc[src]; in pack_uniform_registers()
766 inst->src[i].swizzle += BRW_SWIZZLE4(chan, chan, chan, chan); in pack_uniform_registers()
788 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in opt_algebraic()
789 switch (inst->opcode) { in opt_algebraic()
791 if (inst->src[0].file != IMM) in opt_algebraic()
794 if (inst->saturate) { in opt_algebraic()
795 if (inst->dst.type != inst->src[0].type) in opt_algebraic()
798 if (brw_saturate_immediate(inst->dst.type, in opt_algebraic()
799 &inst->src[0].as_brw_reg())) { in opt_algebraic()
800 inst->saturate = false; in opt_algebraic()
807 if (inst->src[0].file != UNIFORM) { in opt_algebraic()
808 inst->opcode = BRW_OPCODE_MOV; in opt_algebraic()
814 if (inst->src[1].is_zero()) { in opt_algebraic()
815 inst->opcode = BRW_OPCODE_MOV; in opt_algebraic()
816 inst->src[1] = src_reg(); in opt_algebraic()
822 if (inst->src[1].is_zero()) { in opt_algebraic()
823 inst->opcode = BRW_OPCODE_MOV; in opt_algebraic()
824 switch (inst->src[0].type) { in opt_algebraic()
826 inst->src[0] = brw_imm_f(0.0f); in opt_algebraic()
829 inst->src[0] = brw_imm_d(0); in opt_algebraic()
832 inst->src[0] = brw_imm_ud(0u); in opt_algebraic()
837 inst->src[1] = src_reg(); in opt_algebraic()
839 } else if (inst->src[1].is_one()) { in opt_algebraic()
840 inst->opcode = BRW_OPCODE_MOV; in opt_algebraic()
841 inst->src[1] = src_reg(); in opt_algebraic()
843 } else if (inst->src[1].is_negative_one()) { in opt_algebraic()
844 inst->opcode = BRW_OPCODE_MOV; in opt_algebraic()
845 inst->src[0].negate = !inst->src[0].negate; in opt_algebraic()
846 inst->src[1] = src_reg(); in opt_algebraic()
851 if (inst->conditional_mod == BRW_CONDITIONAL_GE && in opt_algebraic()
852 inst->src[0].abs && in opt_algebraic()
853 inst->src[0].negate && in opt_algebraic()
854 inst->src[1].is_zero()) { in opt_algebraic()
855 inst->src[0].abs = false; in opt_algebraic()
856 inst->src[0].negate = false; in opt_algebraic()
857 inst->conditional_mod = BRW_CONDITIONAL_Z; in opt_algebraic()
863 if (is_uniform(inst->src[0]) || in opt_algebraic()
864 inst->src[1].is_zero()) { in opt_algebraic()
865 inst->opcode = BRW_OPCODE_MOV; in opt_algebraic()
866 inst->src[1] = src_reg(); in opt_algebraic()
867 inst->force_writemask_all = true; in opt_algebraic()
946 foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { in move_push_constants_to_pull_constants()
948 if (inst->src[i].file != UNIFORM || in move_push_constants_to_pull_constants()
949 pull_constant_loc[inst->src[i].nr] == -1) in move_push_constants_to_pull_constants()
952 int uniform = inst->src[i].nr; in move_push_constants_to_pull_constants()
954 const glsl_type *temp_type = type_sz(inst->src[i].type) == 8 ? in move_push_constants_to_pull_constants()
958 emit_pull_constant_load(block, inst, temp, inst->src[i], in move_push_constants_to_pull_constants()
961 inst->src[i].file = temp.file; in move_push_constants_to_pull_constants()
962 inst->src[i].nr = temp.nr; in move_push_constants_to_pull_constants()
963 inst->src[i].offset %= 16; in move_push_constants_to_pull_constants()
964 inst->src[i].reladdr = NULL; in move_push_constants_to_pull_constants()
974 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction *inst) in is_dep_ctrl_unsafe() argument
992 if (inst->opcode == BRW_OPCODE_MUL && in is_dep_ctrl_unsafe()
993 IS_DWORD(inst->src[0]) && in is_dep_ctrl_unsafe()
994 IS_DWORD(inst->src[1])) in is_dep_ctrl_unsafe()
999 if (IS_64BIT(inst->dst) || IS_64BIT(inst->src[0]) || in is_dep_ctrl_unsafe()
1000 IS_64BIT(inst->src[1]) || IS_64BIT(inst->src[2])) in is_dep_ctrl_unsafe()
1008 if (inst->opcode == BRW_OPCODE_F32TO16) in is_dep_ctrl_unsafe()
1031 return (inst->mlen || inst->predicate || inst->is_math()); in is_dep_ctrl_unsafe()
1064 foreach_inst_in_block (vec4_instruction, inst, block) { in opt_set_dependency_control()
1069 int reg = inst->src[i].nr + inst->src[i].offset / REG_SIZE; in opt_set_dependency_control()
1070 if (inst->src[i].file == VGRF) { in opt_set_dependency_control()
1072 } else if (inst->src[i].file == FIXED_GRF) { in opt_set_dependency_control()
1076 assert(inst->src[i].file != MRF); in opt_set_dependency_control()
1079 if (is_dep_ctrl_unsafe(inst)) { in opt_set_dependency_control()
1088 int reg = inst->dst.nr + inst->dst.offset / REG_SIZE; in opt_set_dependency_control()
1089 if (inst->dst.file == VGRF || inst->dst.file == FIXED_GRF) { in opt_set_dependency_control()
1091 last_grf_write[reg]->dst.offset == inst->dst.offset && in opt_set_dependency_control()
1092 !(inst->dst.writemask & grf_channels_written[reg])) { in opt_set_dependency_control()
1094 inst->no_dd_check = true; in opt_set_dependency_control()
1099 last_grf_write[reg] = inst; in opt_set_dependency_control()
1100 grf_channels_written[reg] |= inst->dst.writemask; in opt_set_dependency_control()
1101 } else if (inst->dst.file == MRF) { in opt_set_dependency_control()
1103 last_mrf_write[reg]->dst.offset == inst->dst.offset && in opt_set_dependency_control()
1104 !(inst->dst.writemask & mrf_channels_written[reg])) { in opt_set_dependency_control()
1106 inst->no_dd_check = true; in opt_set_dependency_control()
1111 last_mrf_write[reg] = inst; in opt_set_dependency_control()
1112 mrf_channels_written[reg] |= inst->dst.writemask; in opt_set_dependency_control()
1201 foreach_block_and_inst_safe (block, vec4_instruction, inst, cfg) { in opt_register_coalesce()
1205 if (inst->opcode != BRW_OPCODE_MOV || in opt_register_coalesce()
1206 (inst->dst.file != VGRF && inst->dst.file != MRF) || in opt_register_coalesce()
1207 inst->predicate || in opt_register_coalesce()
1208 inst->src[0].file != VGRF || in opt_register_coalesce()
1209 inst->dst.type != inst->src[0].type || in opt_register_coalesce()
1210 inst->src[0].abs || inst->src[0].negate || inst->src[0].reladdr) in opt_register_coalesce()
1214 if (inst->dst.file == inst->src[0].file && in opt_register_coalesce()
1215 inst->dst.nr == inst->src[0].nr && in opt_register_coalesce()
1216 inst->dst.offset == inst->src[0].offset) { in opt_register_coalesce()
1220 if ((inst->dst.writemask & (1 << c)) == 0) in opt_register_coalesce()
1223 if (BRW_GET_SWZ(inst->src[0].swizzle, c) != c) { in opt_register_coalesce()
1230 inst->remove(block); in opt_register_coalesce()
1236 bool to_mrf = (inst->dst.file == MRF); in opt_register_coalesce()
1241 if (var_range_end(var_from_reg(alloc, dst_reg(inst->src[0])), 8) > ip) in opt_register_coalesce()
1250 brw_apply_inv_swizzle_to_mask(inst->src[0].swizzle, in opt_register_coalesce()
1251 inst->dst.writemask); in opt_register_coalesce()
1258 vec4_instruction *_scan_inst = (vec4_instruction *)inst->prev; in opt_register_coalesce()
1260 inst) { in opt_register_coalesce()
1263 if (regions_overlap(inst->src[0], inst->size_read(0), in opt_register_coalesce()
1286 if (inst->saturate && in opt_register_coalesce()
1287 inst->dst.type != scan_inst->dst.type && in opt_register_coalesce()
1296 if (type_sz(inst->src[0].type) != type_sz(scan_inst->src[0].type)) in opt_register_coalesce()
1303 if (scan_inst->size_written != inst->size_written) in opt_register_coalesce()
1307 if (!scan_inst->can_reswizzle(devinfo, inst->dst.writemask, in opt_register_coalesce()
1308 inst->src[0].swizzle, in opt_register_coalesce()
1319 scan_inst->dst.offset != inst->src[0].offset) in opt_register_coalesce()
1337 if (regions_overlap(inst->src[0], inst->size_read(0), in opt_register_coalesce()
1347 if (regions_overlap(inst->dst, inst->size_written, in opt_register_coalesce()
1349 (inst->dst.writemask & scan_inst->dst.writemask) != 0) { in opt_register_coalesce()
1358 if (inst->dst.nr >= scan_inst->base_mrf && in opt_register_coalesce()
1359 inst->dst.nr < scan_inst->base_mrf + scan_inst->mlen) { in opt_register_coalesce()
1364 if (regions_overlap(inst->dst, inst->size_written, in opt_register_coalesce()
1380 while (scan_inst != inst) { in opt_register_coalesce()
1382 scan_inst->dst.nr == inst->src[0].nr && in opt_register_coalesce()
1383 scan_inst->dst.offset == inst->src[0].offset) { in opt_register_coalesce()
1384 scan_inst->reswizzle(inst->dst.writemask, in opt_register_coalesce()
1385 inst->src[0].swizzle); in opt_register_coalesce()
1386 scan_inst->dst.file = inst->dst.file; in opt_register_coalesce()
1387 scan_inst->dst.nr = inst->dst.nr; in opt_register_coalesce()
1388 scan_inst->dst.offset = inst->dst.offset; in opt_register_coalesce()
1389 if (inst->saturate && in opt_register_coalesce()
1390 inst->dst.type != scan_inst->dst.type) { in opt_register_coalesce()
1396 scan_inst->dst.type = inst->dst.type; in opt_register_coalesce()
1397 scan_inst->src[0].type = inst->src[0].type; in opt_register_coalesce()
1399 scan_inst->saturate |= inst->saturate; in opt_register_coalesce()
1403 inst->remove(block); in opt_register_coalesce()
1433 foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { in eliminate_find_live_channel()
1434 switch (inst->opcode) { in eliminate_find_live_channel()
1447 inst->opcode = BRW_OPCODE_MOV; in eliminate_find_live_channel()
1448 inst->src[0] = brw_imm_d(0); in eliminate_find_live_channel()
1449 inst->force_writemask_all = true; in eliminate_find_live_channel()
1491 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in split_virtual_grfs()
1492 if (inst->dst.file == VGRF && regs_written(inst) > 1) in split_virtual_grfs()
1493 split_grf[inst->dst.nr] = false; in split_virtual_grfs()
1496 if (inst->src[i].file == VGRF && regs_read(inst, i) > 1) in split_virtual_grfs()
1497 split_grf[inst->src[i].nr] = false; in split_virtual_grfs()
1517 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in split_virtual_grfs()
1518 if (inst->dst.file == VGRF && split_grf[inst->dst.nr] && in split_virtual_grfs()
1519 inst->dst.offset / REG_SIZE != 0) { in split_virtual_grfs()
1520 inst->dst.nr = (new_virtual_grf[inst->dst.nr] + in split_virtual_grfs()
1521 inst->dst.offset / REG_SIZE - 1); in split_virtual_grfs()
1522 inst->dst.offset %= REG_SIZE; in split_virtual_grfs()
1525 if (inst->src[i].file == VGRF && split_grf[inst->src[i].nr] && in split_virtual_grfs()
1526 inst->src[i].offset / REG_SIZE != 0) { in split_virtual_grfs()
1527 inst->src[i].nr = (new_virtual_grf[inst->src[i].nr] + in split_virtual_grfs()
1528 inst->src[i].offset / REG_SIZE - 1); in split_virtual_grfs()
1529 inst->src[i].offset %= REG_SIZE; in split_virtual_grfs()
1545 vec4_instruction *inst = (vec4_instruction *)be_inst; in dump_instruction() local
1547 if (inst->predicate) { in dump_instruction()
1549 inst->predicate_inverse ? '-' : '+', in dump_instruction()
1550 inst->flag_subreg, in dump_instruction()
1551 pred_ctrl_align16[inst->predicate]); in dump_instruction()
1554 fprintf(file, "%s(%d)", brw_instruction_name(devinfo, inst->opcode), in dump_instruction()
1555 inst->exec_size); in dump_instruction()
1556 if (inst->saturate) in dump_instruction()
1558 if (inst->conditional_mod) { in dump_instruction()
1559 fprintf(file, "%s", conditional_modifier[inst->conditional_mod]); in dump_instruction()
1560 if (!inst->predicate && in dump_instruction()
1561 (devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL && in dump_instruction()
1562 inst->opcode != BRW_OPCODE_IF && in dump_instruction()
1563 inst->opcode != BRW_OPCODE_WHILE))) { in dump_instruction()
1564 fprintf(file, ".f0.%d", inst->flag_subreg); in dump_instruction()
1569 switch (inst->dst.file) { in dump_instruction()
1571 fprintf(file, "vgrf%d", inst->dst.nr); in dump_instruction()
1574 fprintf(file, "g%d", inst->dst.nr); in dump_instruction()
1577 fprintf(file, "m%d", inst->dst.nr); in dump_instruction()
1580 switch (inst->dst.nr) { in dump_instruction()
1585 fprintf(file, "a0.%d", inst->dst.subnr); in dump_instruction()
1588 fprintf(file, "acc%d", inst->dst.subnr); in dump_instruction()
1591 fprintf(file, "f%d.%d", inst->dst.nr & 0xf, inst->dst.subnr); in dump_instruction()
1594 fprintf(file, "arf%d.%d", inst->dst.nr & 0xf, inst->dst.subnr); in dump_instruction()
1606 if (inst->dst.offset || in dump_instruction()
1607 (inst->dst.file == VGRF && in dump_instruction()
1608 alloc.sizes[inst->dst.nr] * REG_SIZE != inst->size_written)) { in dump_instruction()
1609 const unsigned reg_size = (inst->dst.file == UNIFORM ? 16 : REG_SIZE); in dump_instruction()
1610 fprintf(file, "+%d.%d", inst->dst.offset / reg_size, in dump_instruction()
1611 inst->dst.offset % reg_size); in dump_instruction()
1613 if (inst->dst.writemask != WRITEMASK_XYZW) { in dump_instruction()
1615 if (inst->dst.writemask & 1) in dump_instruction()
1617 if (inst->dst.writemask & 2) in dump_instruction()
1619 if (inst->dst.writemask & 4) in dump_instruction()
1621 if (inst->dst.writemask & 8) in dump_instruction()
1624 fprintf(file, ":%s", brw_reg_type_to_letters(inst->dst.type)); in dump_instruction()
1626 if (inst->src[0].file != BAD_FILE) in dump_instruction()
1629 for (int i = 0; i < 3 && inst->src[i].file != BAD_FILE; i++) { in dump_instruction()
1630 if (inst->src[i].negate) in dump_instruction()
1632 if (inst->src[i].abs) in dump_instruction()
1634 switch (inst->src[i].file) { in dump_instruction()
1636 fprintf(file, "vgrf%d", inst->src[i].nr); in dump_instruction()
1639 fprintf(file, "g%d.%d", inst->src[i].nr, inst->src[i].subnr); in dump_instruction()
1642 fprintf(file, "attr%d", inst->src[i].nr); in dump_instruction()
1645 fprintf(file, "u%d", inst->src[i].nr); in dump_instruction()
1648 switch (inst->src[i].type) { in dump_instruction()
1650 fprintf(file, "%fF", inst->src[i].f); in dump_instruction()
1653 fprintf(file, "%fDF", inst->src[i].df); in dump_instruction()
1656 fprintf(file, "%dD", inst->src[i].d); in dump_instruction()
1659 fprintf(file, "%uU", inst->src[i].ud); in dump_instruction()
1663 brw_vf_to_float((inst->src[i].ud >> 0) & 0xff), in dump_instruction()
1664 brw_vf_to_float((inst->src[i].ud >> 8) & 0xff), in dump_instruction()
1665 brw_vf_to_float((inst->src[i].ud >> 16) & 0xff), in dump_instruction()
1666 brw_vf_to_float((inst->src[i].ud >> 24) & 0xff)); in dump_instruction()
1674 switch (inst->src[i].nr) { in dump_instruction()
1679 fprintf(file, "a0.%d", inst->src[i].subnr); in dump_instruction()
1682 fprintf(file, "acc%d", inst->src[i].subnr); in dump_instruction()
1685 fprintf(file, "f%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr); in dump_instruction()
1688 fprintf(file, "arf%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr); in dump_instruction()
1699 if (inst->src[i].offset || in dump_instruction()
1700 (inst->src[i].file == VGRF && in dump_instruction()
1701 alloc.sizes[inst->src[i].nr] * REG_SIZE != inst->size_read(i))) { in dump_instruction()
1702 const unsigned reg_size = (inst->src[i].file == UNIFORM ? 16 : REG_SIZE); in dump_instruction()
1703 fprintf(file, "+%d.%d", inst->src[i].offset / reg_size, in dump_instruction()
1704 inst->src[i].offset % reg_size); in dump_instruction()
1707 if (inst->src[i].file != IMM) { in dump_instruction()
1711 fprintf(file, "%s", chans[BRW_GET_SWZ(inst->src[i].swizzle, c)]); in dump_instruction()
1715 if (inst->src[i].abs) in dump_instruction()
1718 if (inst->src[i].file != IMM) { in dump_instruction()
1719 fprintf(file, ":%s", brw_reg_type_to_letters(inst->src[i].type)); in dump_instruction()
1722 if (i < 2 && inst->src[i + 1].file != BAD_FILE) in dump_instruction()
1726 if (inst->force_writemask_all) in dump_instruction()
1729 if (inst->exec_size != 8) in dump_instruction()
1730 fprintf(file, " group%d", inst->group); in dump_instruction()
1739 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in setup_attributes()
1741 if (inst->src[i].file == ATTR) { in setup_attributes()
1742 assert(inst->src[i].offset % REG_SIZE == 0); in setup_attributes()
1743 int grf = payload_reg + inst->src[i].nr + in setup_attributes()
1744 inst->src[i].offset / REG_SIZE; in setup_attributes()
1747 reg.swizzle = inst->src[i].swizzle; in setup_attributes()
1748 reg.type = inst->src[i].type; in setup_attributes()
1749 reg.abs = inst->src[i].abs; in setup_attributes()
1750 reg.negate = inst->src[i].negate; in setup_attributes()
1751 inst->src[i] = reg; in setup_attributes()
1816 foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { in lower_minmax()
1817 const vec4_builder ibld(this, block, inst); in lower_minmax()
1819 if (inst->opcode == BRW_OPCODE_SEL && in lower_minmax()
1820 inst->predicate == BRW_PREDICATE_NONE) { in lower_minmax()
1824 ibld.CMP(ibld.null_reg_d(), inst->src[0], inst->src[1], in lower_minmax()
1825 inst->conditional_mod); in lower_minmax()
1826 inst->predicate = BRW_PREDICATE_NORMAL; in lower_minmax()
1827 inst->conditional_mod = BRW_CONDITIONAL_NONE; in lower_minmax()
1926 vec4_instruction *inst = in emit_shader_time_write() local
1928 inst->mlen = 2; in emit_shader_time_write()
1932 is_align1_df(vec4_instruction *inst) in is_align1_df() argument
1934 switch (inst->opcode) { in is_align1_df()
1958 foreach_block_and_inst_safe (block, vec4_instruction, inst, cfg) { in fixup_3src_null_dest()
1959 if (inst->is_3src(devinfo) && inst->dst.is_null()) { in fixup_3src_null_dest()
1960 const unsigned size_written = type_sz(inst->dst.type); in fixup_3src_null_dest()
1963 inst->dst = retype(dst_reg(VGRF, alloc.allocate(num_regs)), in fixup_3src_null_dest()
1964 inst->dst.type); in fixup_3src_null_dest()
1976 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in convert_to_hw_regs()
1978 class src_reg &src = inst->src[i]; in convert_to_hw_regs()
2025 apply_logical_swizzle(®, inst, i); in convert_to_hw_regs()
2039 if (is_align1_df(inst) && (cvt(inst->exec_size) - 1) == src.width) in convert_to_hw_regs()
2043 if (inst->is_3src(devinfo)) { in convert_to_hw_regs()
2050 if (inst->src[i].vstride == BRW_VERTICAL_STRIDE_0 && in convert_to_hw_regs()
2051 type_sz(inst->src[i].type) < 8) { in convert_to_hw_regs()
2052 assert(brw_is_single_value_swizzle(inst->src[i].swizzle)); in convert_to_hw_regs()
2053 inst->src[i].subnr += 4 * BRW_GET_SWZ(inst->src[i].swizzle, 0); in convert_to_hw_regs()
2058 dst_reg &dst = inst->dst; in convert_to_hw_regs()
2061 switch (inst->dst.file) { in convert_to_hw_regs()
2118 unsigned stage, const vec4_instruction *inst) in get_lowered_simd_width() argument
2121 switch (inst->opcode) { in get_lowered_simd_width()
2124 return inst->exec_size; in get_lowered_simd_width()
2129 unsigned lowered_width = MIN2(16, inst->exec_size); in get_lowered_simd_width()
2135 if (devinfo->gen == 7 && inst->size_written > REG_SIZE) { in get_lowered_simd_width()
2139 if (inst->opcode == BRW_OPCODE_SEL && type_sz(inst->dst.type) == 8) in get_lowered_simd_width()
2149 if (inst->src[i].file == BAD_FILE) in get_lowered_simd_width()
2151 if (inst->size_read(i) <= REG_SIZE) in get_lowered_simd_width()
2158 if (inst->src[i].file == ATTR && in get_lowered_simd_width()
2171 (get_exec_type_size(inst) == 8 || type_sz(inst->dst.type) == 8)) in get_lowered_simd_width()
2178 dst_src_regions_overlap(vec4_instruction *inst) in dst_src_regions_overlap() argument
2180 if (inst->size_written == 0) in dst_src_regions_overlap()
2183 unsigned dst_start = inst->dst.offset; in dst_src_regions_overlap()
2184 unsigned dst_end = dst_start + inst->size_written - 1; in dst_src_regions_overlap()
2186 if (inst->src[i].file == BAD_FILE) in dst_src_regions_overlap()
2189 if (inst->dst.file != inst->src[i].file || in dst_src_regions_overlap()
2190 inst->dst.nr != inst->src[i].nr) in dst_src_regions_overlap()
2193 unsigned src_start = inst->src[i].offset; in dst_src_regions_overlap()
2194 unsigned src_end = src_start + inst->size_read(i) - 1; in dst_src_regions_overlap()
2211 foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { in lower_simd_width()
2213 get_lowered_simd_width(devinfo, prog_data->dispatch_mode, stage, inst); in lower_simd_width()
2214 assert(lowered_width <= inst->exec_size); in lower_simd_width()
2215 if (lowered_width == inst->exec_size) in lower_simd_width()
2230 bool needs_temp = dst_src_regions_overlap(inst); in lower_simd_width()
2231 for (unsigned n = 0; n < inst->exec_size / lowered_width; n++) { in lower_simd_width()
2234 unsigned size_written = lowered_width * type_sz(inst->dst.type); in lower_simd_width()
2240 vec4_instruction *linst = new(mem_ctx) vec4_instruction(*inst); in lower_simd_width()
2250 inst->dst.type); in lower_simd_width()
2251 if (inst->is_align1_partial_write()) { in lower_simd_width()
2252 vec4_instruction *copy = MOV(dst, src_reg(inst->dst)); in lower_simd_width()
2256 inst->insert_before(block, copy); in lower_simd_width()
2259 dst = horiz_offset(inst->dst, channel_offset); in lower_simd_width()
2277 inst->insert_before(block, linst); in lower_simd_width()
2284 MOV(offset(inst->dst, lowered_width, n), src_reg(dst)); in lower_simd_width()
2288 mov->predicate = inst->predicate; in lower_simd_width()
2289 inst->insert_before(block, mov); in lower_simd_width()
2293 inst->remove(block); in lower_simd_width()
2327 is_gen7_supported_64bit_swizzle(vec4_instruction *inst, unsigned arg) in is_gen7_supported_64bit_swizzle() argument
2329 switch (inst->src[arg].swizzle) { in is_gen7_supported_64bit_swizzle()
2357 vec4_visitor::is_supported_64bit_region(vec4_instruction *inst, unsigned arg) in is_supported_64bit_region() argument
2359 const src_reg &src = inst->src[arg]; in is_supported_64bit_region()
2381 return devinfo->gen == 7 && is_gen7_supported_64bit_swizzle(inst, arg); in is_supported_64bit_region()
2390 foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { in scalarize_df()
2392 if (is_align1_df(inst)) in scalarize_df()
2396 bool is_double = type_sz(inst->dst.type) == 8; in scalarize_df()
2398 is_double = inst->src[arg].file != BAD_FILE && in scalarize_df()
2399 type_sz(inst->src[arg].type) == 8; in scalarize_df()
2413 if (inst->dst.writemask == WRITEMASK_XY || in scalarize_df()
2414 inst->dst.writemask == WRITEMASK_ZW) { in scalarize_df()
2418 if (inst->src[i].file == BAD_FILE || type_sz(inst->src[i].type) < 8) in scalarize_df()
2420 skip_lowering = skip_lowering && is_supported_64bit_region(inst, i); in scalarize_df()
2430 if (!(inst->dst.writemask & chan_mask)) in scalarize_df()
2433 vec4_instruction *scalar_inst = new(mem_ctx) vec4_instruction(*inst); in scalarize_df()
2436 unsigned swz = BRW_GET_SWZ(inst->src[i].swizzle, chan); in scalarize_df()
2442 if (inst->predicate != BRW_PREDICATE_NONE) { in scalarize_df()
2444 scalarize_predicate(inst->predicate, chan_mask); in scalarize_df()
2447 inst->insert_before(block, scalar_inst); in scalarize_df()
2450 inst->remove(block); in scalarize_df()
2465 foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { in lower_64bit_mad_to_mul_add()
2466 if (inst->opcode != BRW_OPCODE_MAD) in lower_64bit_mad_to_mul_add()
2469 if (type_sz(inst->dst.type) != 8) in lower_64bit_mad_to_mul_add()
2477 vec4_instruction *mul = new(mem_ctx) vec4_instruction(*inst); in lower_64bit_mad_to_mul_add()
2480 mul->src[0] = inst->src[1]; in lower_64bit_mad_to_mul_add()
2481 mul->src[1] = inst->src[2]; in lower_64bit_mad_to_mul_add()
2484 vec4_instruction *add = new(mem_ctx) vec4_instruction(*inst); in lower_64bit_mad_to_mul_add()
2487 add->src[1] = inst->src[0]; in lower_64bit_mad_to_mul_add()
2490 inst->insert_before(block, mul); in lower_64bit_mad_to_mul_add()
2491 inst->insert_before(block, add); in lower_64bit_mad_to_mul_add()
2492 inst->remove(block); in lower_64bit_mad_to_mul_add()
2517 vec4_instruction *inst, int arg) in apply_logical_swizzle() argument
2519 src_reg reg = inst->src[arg]; in apply_logical_swizzle()
2527 if(type_sz(reg.type) < 8 || is_align1_df(inst)) { in apply_logical_swizzle()
2534 is_supported_64bit_region(inst, arg)); in apply_logical_swizzle()
2541 if (is_supported_64bit_region(inst, arg) && in apply_logical_swizzle()
2542 !is_gen7_supported_64bit_swizzle(inst, arg)) { in apply_logical_swizzle()
2575 if (devinfo->gen == 7 && is_gen7_supported_64bit_swizzle(inst, arg)) in apply_logical_swizzle()