150 vec4_instruction::is_send_from_grf()  in is_send_from_grf()
191 vec4_instruction::has_source_and_destination_hazard() const  in has_source_and_destination_hazard()
210 vec4_instruction::size_read(unsigned arg) const  in size_read()
245 vec4_instruction::can_do_source_mods(const struct gen_device_info *devinfo)  in can_do_source_mods()
260 vec4_instruction::can_do_writemask(const struct gen_device_info *devinfo)  in can_do_writemask()
297 vec4_instruction::can_change_types() const  in can_change_types()
316 vec4_visitor::implied_mrf_writes(vec4_instruction *inst)  in implied_mrf_writes()
389       vec4_instruction *imm_inst[4];  in opt_vector_float()
393       foreach_inst_in_block_safe(vec4_instruction, inst, block) {  in opt_vector_float()
432                vec4_instruction *mov = MOV(imm_inst[0]->dst, brw_imm_vf(vf));  in opt_vector_float()
501    foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {  in opt_reduce_swizzle()
574    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {  in split_uniform_registers()
632    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {  in pack_uniform_registers()
757    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {  in pack_uniform_registers()
788    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {  in opt_algebraic()
946    foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {  in move_push_constants_to_pull_constants()
974 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction *inst)  in is_dep_ctrl_unsafe()
1052    vec4_instruction *last_grf_write[BRW_MAX_GRF];  in opt_set_dependency_control()
1054    vec4_instruction *last_mrf_write[BRW_MAX_GRF];  in opt_set_dependency_control()
1064       foreach_inst_in_block (vec4_instruction, inst, block) {  in opt_set_dependency_control()
1119 vec4_instruction::can_reswizzle(const struct gen_device_info *devinfo,  in can_reswizzle()
1165 vec4_instruction::reswizzle(int dst_writemask, int swizzle)  in reswizzle()
1201    foreach_block_and_inst_safe (block, vec4_instruction, inst, cfg) {  in opt_register_coalesce()
1258       vec4_instruction *_scan_inst = (vec4_instruction *)inst->prev;  in opt_register_coalesce()
1259       foreach_inst_in_block_reverse_starting_from(vec4_instruction, scan_inst,  in opt_register_coalesce()
1379          vec4_instruction *scan_inst = _scan_inst;  in opt_register_coalesce()
1401 	    scan_inst = (vec4_instruction *)scan_inst->next;  in opt_register_coalesce()
1433    foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {  in eliminate_find_live_channel()
1491    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {  in split_virtual_grfs()
1517    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {  in split_virtual_grfs()
1545    vec4_instruction *inst = (vec4_instruction *)be_inst;  in dump_instruction()
1739    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {  in setup_attributes()
1816    foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {  in lower_minmax()
1858    vec4_instruction *mov = emit(MOV(dst, ts));  in get_timestamp()
1886    vec4_instruction *test = emit(AND(dst_null_ud(), reset_end, brw_imm_ud(1u)));  in emit_shader_time_end()
1926    vec4_instruction *inst =  in emit_shader_time_write()
1932 is_align1_df(vec4_instruction *inst)  in is_align1_df()
1958    foreach_block_and_inst_safe (block, vec4_instruction, inst, cfg) {  in fixup_3src_null_dest()
1976    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {  in convert_to_hw_regs()
2118                        unsigned stage, const vec4_instruction *inst)  in get_lowered_simd_width()
2178 dst_src_regions_overlap(vec4_instruction *inst)  in dst_src_regions_overlap()
2211    foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {  in lower_simd_width()
2240          vec4_instruction *linst = new(mem_ctx) vec4_instruction(*inst);  in lower_simd_width()
2252                vec4_instruction *copy = MOV(dst, src_reg(inst->dst));  in lower_simd_width()
2283             vec4_instruction *mov =  in lower_simd_width()
2327 is_gen7_supported_64bit_swizzle(vec4_instruction *inst, unsigned arg)  in is_gen7_supported_64bit_swizzle()
2357 vec4_visitor::is_supported_64bit_region(vec4_instruction *inst, unsigned arg)  in is_supported_64bit_region()
2390    foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {  in scalarize_df()
2433          vec4_instruction *scalar_inst = new(mem_ctx) vec4_instruction(*inst);  in scalarize_df()
2465    foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {  in lower_64bit_mad_to_mul_add()
2477       vec4_instruction *mul = new(mem_ctx) vec4_instruction(*inst);  in lower_64bit_mad_to_mul_add()
2484       vec4_instruction *add = new(mem_ctx) vec4_instruction(*inst);  in lower_64bit_mad_to_mul_add()
2517                                     vec4_instruction *inst, int arg)  in apply_logical_swizzle()