Lines Matching refs:tile_info
160 struct isl_tile_info *tile_info) in isl_tiling_get_info() argument
173 isl_tiling_get_info(tiling, format_bpb / 3, tile_info); in isl_tiling_get_info()
263 *tile_info = (struct isl_tile_info) { in isl_tiling_get_info()
810 const struct isl_tile_info *tile_info, in isl_calc_array_pitch_el_rows_gen4_2d() argument
892 tile_info->tiling != ISL_TILING_LINEAR) { in isl_calc_array_pitch_el_rows_gen4_2d()
898 pitch_el_rows = isl_align(pitch_el_rows, tile_info->logical_extent_el.height); in isl_calc_array_pitch_el_rows_gen4_2d()
984 const struct isl_tile_info *tile_info, in isl_calc_phys_total_extent_el_gen4_2d() argument
999 isl_calc_array_pitch_el_rows_gen4_2d(dev, info, tile_info, in isl_calc_phys_total_extent_el_gen4_2d()
1082 const struct isl_tile_info *tile_info, in isl_calc_phys_total_extent_el_gen6_stencil_hiz() argument
1091 .w = tile_info->logical_extent_el.w * fmtl->bw, in isl_calc_phys_total_extent_el_gen6_stencil_hiz()
1092 .h = tile_info->logical_extent_el.h * fmtl->bh, in isl_calc_phys_total_extent_el_gen6_stencil_hiz()
1179 const struct isl_tile_info *tile_info, in isl_calc_phys_total_extent_el() argument
1197 isl_calc_phys_total_extent_el_gen4_2d(dev, info, tile_info, msaa_layout, in isl_calc_phys_total_extent_el()
1205 isl_calc_phys_total_extent_el_gen6_stencil_hiz(dev, info, tile_info, in isl_calc_phys_total_extent_el()
1223 const struct isl_tile_info *tile_info) in isl_calc_row_pitch_alignment() argument
1225 if (tile_info->tiling != ISL_TILING_LINEAR) in isl_calc_row_pitch_alignment()
1226 return tile_info->phys_extent_B.width; in isl_calc_row_pitch_alignment()
1271 const struct isl_tile_info *tile_info, in isl_calc_tiled_min_row_pitch() argument
1277 assert(fmtl->bpb % tile_info->format_bpb == 0); in isl_calc_tiled_min_row_pitch()
1279 const uint32_t tile_el_scale = fmtl->bpb / tile_info->format_bpb; in isl_calc_tiled_min_row_pitch()
1282 tile_info->logical_extent_el.width); in isl_calc_tiled_min_row_pitch()
1284 assert(alignment == tile_info->phys_extent_B.width); in isl_calc_tiled_min_row_pitch()
1285 return total_w_tl * tile_info->phys_extent_B.width; in isl_calc_tiled_min_row_pitch()
1291 const struct isl_tile_info *tile_info, in isl_calc_min_row_pitch() argument
1295 if (tile_info->tiling == ISL_TILING_LINEAR) { in isl_calc_min_row_pitch()
1299 return isl_calc_tiled_min_row_pitch(dev, surf_info, tile_info, in isl_calc_min_row_pitch()
1323 const struct isl_tile_info *tile_info, in isl_calc_row_pitch() argument
1329 isl_calc_row_pitch_alignment(surf_info, tile_info); in isl_calc_row_pitch()
1334 if (surf_info->row_pitch == 0 && tile_info->tiling == ISL_TILING_LINEAR) { in isl_calc_row_pitch()
1346 isl_calc_min_row_pitch(dev, surf_info, tile_info, phys_total_el, in isl_calc_row_pitch()
1361 const uint32_t row_pitch_tiles = row_pitch / tile_info->phys_extent_B.width; in isl_calc_row_pitch()
1421 struct isl_tile_info tile_info; in isl_surf_init_s() local
1422 isl_tiling_get_info(tiling, fmtl->bpb, &tile_info); in isl_surf_init_s()
1449 isl_calc_phys_total_extent_el(dev, info, &tile_info, in isl_surf_init_s()
1456 if (!isl_calc_row_pitch(dev, info, &tile_info, dim_layout, in isl_surf_init_s()
1485 isl_align_div(phys_total_el.h, tile_info.logical_extent_el.height); in isl_surf_init_s()
1487 size = (uint64_t) total_h_tl * tile_info.phys_extent_B.height * row_pitch; in isl_surf_init_s()
1489 const uint32_t tile_size = tile_info.phys_extent_B.width * in isl_surf_init_s()
1490 tile_info.phys_extent_B.height; in isl_surf_init_s()
1545 struct isl_tile_info *tile_info) in isl_surf_get_tile_info() argument
1548 isl_tiling_get_info(surf->tiling, fmtl->bpb, tile_info); in isl_surf_get_tile_info()
1993 struct isl_tile_info tile_info; in get_image_offset_sa_gen6_stencil_hiz() local
1994 isl_tiling_get_info(surf->tiling, fmtl->bpb, &tile_info); in get_image_offset_sa_gen6_stencil_hiz()
1996 .w = tile_info.logical_extent_el.w * fmtl->bw, in get_image_offset_sa_gen6_stencil_hiz()
1997 .h = tile_info.logical_extent_el.h * fmtl->bh, in get_image_offset_sa_gen6_stencil_hiz()
2241 struct isl_tile_info tile_info; in isl_tiling_get_intratile_offset_el() local
2242 isl_tiling_get_info(tiling, bpb, &tile_info); in isl_tiling_get_intratile_offset_el()
2244 assert(row_pitch % tile_info.phys_extent_B.width == 0); in isl_tiling_get_intratile_offset_el()
2255 const uint32_t tile_el_scale = bpb / tile_info.format_bpb; in isl_tiling_get_intratile_offset_el()
2256 tile_info.phys_extent_B.width *= tile_el_scale; in isl_tiling_get_intratile_offset_el()
2259 *x_offset_el = total_x_offset_el % tile_info.logical_extent_el.w; in isl_tiling_get_intratile_offset_el()
2260 *y_offset_el = total_y_offset_el % tile_info.logical_extent_el.h; in isl_tiling_get_intratile_offset_el()
2263 uint32_t x_offset_tl = total_x_offset_el / tile_info.logical_extent_el.w; in isl_tiling_get_intratile_offset_el()
2264 uint32_t y_offset_tl = total_y_offset_el / tile_info.logical_extent_el.h; in isl_tiling_get_intratile_offset_el()
2267 y_offset_tl * tile_info.phys_extent_B.h * row_pitch + in isl_tiling_get_intratile_offset_el()
2268 x_offset_tl * tile_info.phys_extent_B.h * tile_info.phys_extent_B.w; in isl_tiling_get_intratile_offset_el()