49    anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {  in gen10_emit_wa_cs_stall_flush()
69    anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {  in gen10_emit_wa_lri_to_cache_mode_zero()
82    anv_pack_struct(&cache_mode_0, GENX(CACHE_MODE_0));  in gen10_emit_wa_lri_to_cache_mode_zero()
84    anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {  in gen10_emit_wa_lri_to_cache_mode_zero()
85       lri.RegisterOffset = GENX(CACHE_MODE_0_num);  in gen10_emit_wa_lri_to_cache_mode_zero()
94    GENX(MEMORY_OBJECT_CONTROL_STATE_pack)(NULL, &device->default_mocs,  in genX()
95                                           &GENX(MOCS));  in genX()
103    anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {  in genX()
112    anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1),  in genX()
118    anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {  in genX()
119       lri.RegisterOffset = GENX(CACHE_MODE_1_num);  in genX()
126    anv_pack_struct(&cache_mode_ss, GENX(CACHE_MODE_SS),  in genX()
130    anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {  in genX()
131       lri.RegisterOffset = GENX(CACHE_MODE_SS_num);  in genX()
136    anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);  in genX()
138    anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {  in genX()
148    anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck);  in genX()
157    anv_batch_emit(&batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) {  in genX()
172    anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);  in genX()
292       struct GENX(SAMPLER_STATE) sampler_state = {  in genX()
338       GENX(SAMPLER_STATE_pack)(NULL, sampler->state[p], &sampler_state);  in genX()