68 #define VREG_INT_COUNT       8  macro
71 #define VREG_INT_COUNT       4  macro
75 #define PARALLEL_COLS_53     (2*VREG_INT_COUNT)
641         STOREU(&tiledp_col[(OPJ_SIZE_T)i * stride + VREG_INT_COUNT],  in opj_idwt53_v_final_memcpy()
642                LOAD(&tmp[PARALLEL_COLS_53 * i + VREG_INT_COUNT]));  in opj_idwt53_v_final_memcpy()
667     assert(VREG_INT_COUNT == 8);  in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
670     assert(VREG_INT_COUNT == 4);  in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
676     assert((OPJ_SIZE_T)tmp % (sizeof(OPJ_INT32) * VREG_INT_COUNT) == 0);  in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
679     s1n_1 = LOADU(in_even + VREG_INT_COUNT);  in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
681     d1n_1 = LOADU(in_odd + VREG_INT_COUNT);  in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
695         s1n_1 = LOADU(in_even + j * stride + VREG_INT_COUNT);  in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
697         d1n_1 = LOADU(in_odd + j * stride + VREG_INT_COUNT);  in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
704         STORE(tmp + PARALLEL_COLS_53 * (i + 0) + VREG_INT_COUNT, s0c_1);  in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
709         STORE(tmp + PARALLEL_COLS_53 * (i + 1) + VREG_INT_COUNT,  in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
714     STORE(tmp + PARALLEL_COLS_53 * (i + 0) + VREG_INT_COUNT, s0n_1);  in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
726         s1n_1 = LOADU(in_even + (OPJ_SIZE_T)((len - 1) / 2) * stride + VREG_INT_COUNT);  in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
729         STORE(tmp + PARALLEL_COLS_53 * (len - 1) + VREG_INT_COUNT,  in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
732         STORE(tmp + PARALLEL_COLS_53 * (len - 2) + VREG_INT_COUNT,  in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
739         STORE(tmp + PARALLEL_COLS_53 * (len - 1) + VREG_INT_COUNT,  in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
769     assert(VREG_INT_COUNT == 8);  in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()
772     assert(VREG_INT_COUNT == 4);  in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()
778     assert((OPJ_SIZE_T)tmp % (sizeof(OPJ_INT32) * VREG_INT_COUNT) == 0);  in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()
786     s1_1 = LOADU(in_even + stride + VREG_INT_COUNT);  in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()
788     dc_1 = SUB(LOADU(in_odd + VREG_INT_COUNT),  in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()
789                SAR(ADD3(LOADU(in_even + VREG_INT_COUNT), s1_1, two), 2));  in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()
790     STORE(tmp + PARALLEL_COLS_53 * 0 + VREG_INT_COUNT,  in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()
791           ADD(LOADU(in_even + VREG_INT_COUNT), dc_1));  in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()
796         s2_1 = LOADU(in_even + (j + 1) * stride + VREG_INT_COUNT);  in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()
801         dn_1 = SUB(LOADU(in_odd + j * stride + VREG_INT_COUNT),  in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()
805         STORE(tmp + PARALLEL_COLS_53 * i + VREG_INT_COUNT, dc_1);  in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()
810         STORE(tmp + PARALLEL_COLS_53 * (i + 1) + VREG_INT_COUNT,  in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()
819     STORE(tmp + PARALLEL_COLS_53 * i + VREG_INT_COUNT, dc_1);  in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()
825         dn_1 = SUB(LOADU(in_odd + (OPJ_SIZE_T)(len / 2 - 1) * stride + VREG_INT_COUNT),  in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()
831         STORE(tmp + PARALLEL_COLS_53 * (len - 2) + VREG_INT_COUNT,  in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()
835         STORE(tmp + PARALLEL_COLS_53 * (len - 1) + VREG_INT_COUNT, dn_1);  in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()
838         STORE(tmp + PARALLEL_COLS_53 * (len - 1) + VREG_INT_COUNT,  in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()