53   assert(isReg() && "Can only add reg operand to use lists");  in AddRegOperandToRegInfo()
144   if (isReg() && getParent() && getParent()->getParent() &&  in ChangeToImmediate()
160   if (isReg()) {  in ChangeToRegister()
572     assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&  in ~MachineInstr()
592     if (Operands[i].isReg())  in RemoveRegOperandsFromUseLists()
602     if (Operands[i].isReg())  in AddRegOperandsToUseLists()
614   bool isImpReg = Op.isReg() && Op.isImplicit();  in addOperand()
632     while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {  in addOperand()
649       if (Operands[i].isReg())  in addOperand()
660       if (Operands[i].isReg())  in addOperand()
664   if (Operands[OpNo].isReg()) {  in addOperand()
676       assert(Operands[i].isReg() && "Should only be an implicit reg!");  in addOperand()
691     if (Operands.back().isReg() && Operands.back().isOnRegUseList())  in RemoveOperand()
704       if (Operands[i].isReg())  in RemoveOperand()
713       if (Operands[i].isReg())  in RemoveOperand()
750     if (!MO.isReg()) {  in isIdenticalTo()
814     if (!MO.isReg() || !MO.isImplicit())  in getNumExplicitOperands()
865   if (!getOperand(OpIdx).isReg())  in getRegClassConstraint()
897     if (!MO.isReg() || !MO.isUse())  in findRegisterUseOperandIdx()
925     if (!MO.isReg() || MO.getReg() != Reg)  in readsWritesVirtualRegister()
951     if (!MO.isReg() || !MO.isDef())  in findRegisterDefOperandIdx()
995     if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)  in isRegTiedToUseOperand()
1011       if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())  in isRegTiedToUseOperand()
1028     if (MO.isReg() && MO.isUse() &&  in isRegTiedToUseOperand()
1045     if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)  in isRegTiedToDefOperand()
1079   if (!MO.isReg() || !MO.isUse())  in isRegTiedToDefOperand()
1094     if (MO.isReg() && MO.isUse())  in clearKillInfo()
1104     if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))  in copyKillDeadInfo()
1141       if (!MO.isReg() || MO.getReg() != FromReg)  in substituteRegister()
1148       if (!MO.isReg() || MO.getReg() != FromReg)  in substituteRegister()
1195     if (!MO.isReg())  in isSafeToReMat()
1310     if (!MO.isReg() || MO.isUse())  in allDefsAreDead()
1324     if (MO.isReg() && MO.isImplicit())  in copyImplicitOps()
1372   for (; StartOp < e && getOperand(StartOp).isReg() &&  in print()
1415     if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))  in print()
1423         MO.isReg() && MO.isImplicit() && MO.isDef()) {  in print()
1571     if (!MO.isReg() || !MO.isUse() || MO.isUndef())  in addRegisterKilled()
1629     if (!MO.isReg() || !MO.isDef())  in addRegisterDead()
1682       if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&  in addRegisterDefined()
1696     if (!MO.isReg() || !MO.isDef()) continue;  in setPhysRegsDeadExcept()