Lines Matching refs:VirtReg
138 LiveRangeStage getStage(const LiveInterval &VirtReg) const { in getStage()
139 return ExtraRegInfo[VirtReg.reg].Stage; in getStage()
142 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument
144 ExtraRegInfo[VirtReg.reg].Stage = Stage; in setStage()
358 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { in LRE_CanEraseVirtReg() argument
359 if (unsigned PhysReg = VRM->getPhys(VirtReg)) { in LRE_CanEraseVirtReg()
360 unassign(LIS->getInterval(VirtReg), PhysReg); in LRE_CanEraseVirtReg()
368 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg() argument
369 unsigned PhysReg = VRM->getPhys(VirtReg); in LRE_WillShrinkVirtReg()
374 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_WillShrinkVirtReg()
444 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, in tryAssign() argument
450 if (!checkPhysRegInterference(VirtReg, PhysReg)) in tryAssign()
459 if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg)) in tryAssign()
463 if (canEvictInterference(VirtReg, Hint, true, MaxCost)) { in tryAssign()
464 evictInterference(VirtReg, Hint, NewVRegs); in tryAssign()
478 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost); in tryAssign()
521 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, in canEvictInterference() argument
530 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade; in canEvictInterference()
536 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI); in canEvictInterference()
552 bool Urgent = !VirtReg.isSpillable() && Intf->isSpillable(); in canEvictInterference()
571 if (!Urgent && !shouldEvict(VirtReg, IsHint, *Intf, BreaksHint)) in canEvictInterference()
582 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, in evictInterference() argument
587 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade; in evictInterference()
589 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++; in evictInterference()
594 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI); in evictInterference()
600 VirtReg.isSpillable() < Intf->isSpillable()) && in evictInterference()
613 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, in tryEvict() argument
627 BestCost.MaxWeight = VirtReg.weight; in tryEvict()
644 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost)) in tryEvict()
658 evictInterference(VirtReg, BestPhys, NewVRegs); in tryEvict()
1085 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryRegionSplit() argument
1175 LiveRangeEdit LREdit(VirtReg, NewVRegs, this); in tryRegionSplit()
1218 unsigned RAGreedy::tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryBlockSplit() argument
1220 assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed"); in tryBlockSplit()
1221 unsigned Reg = VirtReg.reg; in tryBlockSplit()
1223 LiveRangeEdit LREdit(VirtReg, NewVRegs, this); in tryBlockSplit()
1320 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryLocalSplit() argument
1362 bool ProgressRequired = getStage(VirtReg) >= RS_Split2; in tryLocalSplit()
1469 LiveRangeEdit LREdit(VirtReg, NewVRegs, this); in tryLocalSplit()
1478 DebugVars->splitRegister(VirtReg.reg, LREdit.regs()); in tryLocalSplit()
1508 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order, in trySplit() argument
1511 if (getStage(VirtReg) >= RS_Spill) in trySplit()
1515 if (LIS->intervalIsInOneMBB(VirtReg)) { in trySplit()
1517 SA->analyze(&VirtReg); in trySplit()
1518 return tryLocalSplit(VirtReg, Order, NewVRegs); in trySplit()
1523 SA->analyze(&VirtReg); in trySplit()
1532 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs)) in trySplit()
1539 if (getStage(VirtReg) < RS_Split2) { in trySplit()
1540 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs); in trySplit()
1546 return tryBlockSplit(VirtReg, Order, NewVRegs); in trySplit()
1554 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit() argument
1557 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo); in selectOrSplit()
1558 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs)) in selectOrSplit()
1561 LiveRangeStage Stage = getStage(VirtReg); in selectOrSplit()
1563 << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n'); in selectOrSplit()
1569 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs)) in selectOrSplit()
1578 setStage(VirtReg, RS_Split); in selectOrSplit()
1580 NewVRegs.push_back(&VirtReg); in selectOrSplit()
1586 if (Stage >= RS_Done || !VirtReg.isSpillable()) in selectOrSplit()
1590 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs); in selectOrSplit()
1596 LiveRangeEdit LRE(VirtReg, NewVRegs, this); in selectOrSplit()