55   VirtRegMap *vrm;  member in __anond2c2b0460211::SpillerBase
63   SpillerBase(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)  in SpillerBase()  argument
64     : pass(&pass), mf(&mf), vrm(&vrm)  in SpillerBase()
89     unsigned ss = vrm->assignVirt2StackSlot(li->reg);  in trivialSpillEverywhere()
120       vrm->grow();  in trivialSpillEverywhere()
121       vrm->assignVirt2StackSlot(newVReg, ss);  in trivialSpillEverywhere()
144         vrm->addSpillSlotUse(ss, loadInstr);  in trivialSpillEverywhere()
158         vrm->addSpillSlotUse(ss, storeInstr);  in trivialSpillEverywhere()
180                  VirtRegMap &vrm)  in TrivialSpiller()  argument
181     : SpillerBase(pass, mf, vrm) {}  in TrivialSpiller()
200   VirtRegMap *vrm;  member in __anond2c2b0460411::StandardSpiller
203                   VirtRegMap &vrm)  in StandardSpiller()  argument
208       vrm(&vrm) {}  in StandardSpiller()
214                                  loopInfo, *vrm);  in spill()
219     int SS = vrm->getStackSlot(LRE.getReg());  in spill()
234                                    VirtRegMap &vrm) {  in createSpiller()  argument
237   case trivial: return new TrivialSpiller(pass, mf, vrm);  in createSpiller()
238   case standard: return new StandardSpiller(pass, mf, vrm);  in createSpiller()
239   case inline_: return createInlineSpiller(pass, mf, vrm);  in createSpiller()