Lines Matching refs:RegKills
272 void AddAvailableRegsToLiveIn(MachineBasicBlock &MBB, BitVector &RegKills,
422 BitVector &RegKills,
440 BitVector &RegKills, in GetRegForReload() argument
447 Rejected, RegKills, KillOps, VRM); in GetRegForReload()
474 BitVector &RegKills, in ResurrectConfirmedKill() argument
482 if (!RegKills[KReg]) in ResurrectConfirmedKill()
488 RegKills.reset(KReg); in ResurrectConfirmedKill()
498 RegKills.reset(*SR); in ResurrectConfirmedKill()
519 const TargetRegisterInfo* TRI, BitVector &RegKills, in ResurrectKill() argument
521 if (RegKills[Reg] && KillOps[Reg]->getParent() != &MI) { in ResurrectKill()
522 ResurrectConfirmedKill(Reg, TRI, RegKills, KillOps); in ResurrectKill()
534 if (RegKills[SReg] && KillOps[SReg]->getParent() != &MI) in ResurrectKill()
535 ResurrectConfirmedKill(SReg, TRI, RegKills, KillOps); in ResurrectKill()
543 BitVector &RegKills, in InvalidateKills() argument
559 RegKills.reset(Reg); in InvalidateKills()
561 if (RegKills[*SR]) { in InvalidateKills()
564 RegKills.reset(*SR); in InvalidateKills()
571 ResurrectKill(MI, Reg, TRI, RegKills, KillOps); in InvalidateKills()
627 BitVector &RegKills, in UpdateKills() argument
641 ResurrectKill(MI, Reg, TRI, RegKills, KillOps); in UpdateKills()
644 RegKills.set(Reg); in UpdateKills()
647 RegKills.set(*SR); in UpdateKills()
658 RegKills.reset(Reg); in UpdateKills()
662 RegKills.reset(*SR); in UpdateKills()
666 RegKills.reset(*SR); in UpdateKills()
780 BitVector &RegKills, in AddAvailableRegsToLiveIn() argument
796 if (RegKills[Reg]) in AddAvailableRegsToLiveIn()
797 ResurrectConfirmedKill(Reg, TRI, RegKills, KillOps); in AddAvailableRegsToLiveIn()
871 BitVector &RegKills, in GetRegForReload() argument
893 Rejected, RegKills, KillOps, VRM); in GetRegForReload()
930 Rejected, RegKills, KillOps, VRM); in GetRegForReload()
961 UpdateKills(*prior(InsertLoc), TRI, RegKills, KillOps); in GetRegForReload()
1126 BitVector &RegKills,
1132 BitVector &RegKills,
1138 BitVector &RegKills,
1148 BitVector &RegKills,
1151 void TransferDeadness(unsigned Reg, BitVector &RegKills,
1158 BitVector &RegKills,
1165 BitVector &RegKills,
1170 AvailableSpills &Spills, BitVector &RegKills,
1195 BitVector RegKills(TRI->getNumRegs()); in runOnMachineFunction() local
1212 RewriteMBB(LIs, Spills, RegKills, KillOps); in runOnMachineFunction()
1227 Spills.AddAvailableRegsToLiveIn(*MBB, RegKills, KillOps); in runOnMachineFunction()
1228 RewriteMBB(LIs, Spills, RegKills, KillOps); in runOnMachineFunction()
1279 BitVector &RegKills, in OptimizeByUnfold2() argument
1330 InvalidateKills(MI, TRI, RegKills, KillOps); in OptimizeByUnfold2()
1345 InvalidateKills(NextMI, TRI, RegKills, KillOps); in OptimizeByUnfold2()
1380 BitVector &RegKills, in OptimizeByUnfold() argument
1420 RegKills, KillOps); in OptimizeByUnfold()
1472 InvalidateKills(MI, TRI, RegKills, KillOps); in OptimizeByUnfold()
1521 BitVector &RegKills, in CommuteToFoldReload() argument
1578 InvalidateKills(*ReloadMI, TRI, RegKills, KillOps); in CommuteToFoldReload()
1580 InvalidateKills(*DefMI, TRI, RegKills, KillOps); in CommuteToFoldReload()
1582 InvalidateKills(MI, TRI, RegKills, KillOps); in CommuteToFoldReload()
1606 BitVector &RegKills, in SpillRegToStackSlot() argument
1621 InvalidateKills(*LastStore, TRI, RegKills, KillOps, &KillRegs); in SpillRegToStackSlot()
1692 TransferDeadness(unsigned Reg, BitVector &RegKills, in TransferDeadness() argument
1736 RegKills.set(Reg); in TransferDeadness()
1782 BitVector &RegKills, in InsertRestores() argument
1855 UpdateKills(*CopyMI, TRI, RegKills, KillOps); in InsertRestores()
1883 UpdateKills(*prior(InsertLoc), TRI, RegKills, KillOps); in InsertRestores()
1921 BitVector &RegKills, in ProcessUses() argument
2142 MaybeDeadStores, RegKills, KillOps, *VRM); in ProcessUses()
2175 UpdateKills(*CopyMI, TRI, RegKills, KillOps); in ProcessUses()
2200 Spills, MaybeDeadStores, RegKills, KillOps, *VRM); in ProcessUses()
2237 UpdateKills(*prior(InsertLoc), TRI, RegKills, KillOps); in ProcessUses()
2253 InvalidateKills(*DeadStore, TRI, RegKills, KillOps); in ProcessUses()
2265 AvailableSpills &Spills, BitVector &RegKills, in RewriteMBB() argument
2289 RegKills.reset(); in RewriteMBB()
2298 if (OptimizeByUnfold(MII, MaybeDeadStores, Spills, RegKills, KillOps)) in RewriteMBB()
2304 InsertRestores(MII, Spills, RegKills, KillOps); in RewriteMBB()
2321 ProcessUses(MI, Spills, MaybeDeadStores, RegKills, ReusedOperands, KillOps); in RewriteMBB()
2380 InvalidateKills(MI, TRI, RegKills, KillOps); in RewriteMBB()
2391 InvalidateKills(MI, TRI, RegKills, KillOps); in RewriteMBB()
2427 InvalidateKills(MI, TRI, RegKills, KillOps); in RewriteMBB()
2442 InvalidateKills(*DeadStore, TRI, RegKills, KillOps); in RewriteMBB()
2474 Spills, RegKills, KillOps, TRI)) { in RewriteMBB()
2513 InvalidateKills(MI, TRI, RegKills, KillOps, &KillRegs); in RewriteMBB()
2518 TransferDeadness(MI.getOperand(1).getReg(), RegKills, KillOps); in RewriteMBB()
2573 Spills, MaybeDeadStores, RegKills, KillOps, *VRM); in RewriteMBB()
2591 LastStore, Spills, ReMatDefs, RegKills, KillOps); in RewriteMBB()
2599 InvalidateKills(MI, TRI, RegKills, KillOps); in RewriteMBB()
2602 UpdateKills(*LastStore, TRI, RegKills, KillOps); in RewriteMBB()
2610 InvalidateKills(MI, TRI, RegKills, KillOps); in RewriteMBB()
2618 UpdateKills(*II, TRI, RegKills, KillOps); in RewriteMBB()