Lines Matching refs:OS
30 RegisterInfoEmitter::runEnums(raw_ostream &OS, in runEnums() argument
36 EmitSourceFileHeader("Target Register Enum Values", OS); in runEnums()
38 OS << "\n#ifdef GET_REGINFO_ENUM\n"; in runEnums()
39 OS << "#undef GET_REGINFO_ENUM\n"; in runEnums()
41 OS << "namespace llvm {\n\n"; in runEnums()
43 OS << "class MCRegisterClass;\n" in runEnums()
47 OS << "namespace " << Namespace << " {\n"; in runEnums()
48 OS << "enum {\n NoRegister,\n"; in runEnums()
51 OS << " " << Registers[i]->getName() << " = " << in runEnums()
55 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; in runEnums()
56 OS << "};\n"; in runEnums()
58 OS << "}\n"; in runEnums()
62 OS << "\n// Register classes\n"; in runEnums()
64 OS << "namespace " << Namespace << " {\n"; in runEnums()
65 OS << "enum {\n"; in runEnums()
67 if (i) OS << ",\n"; in runEnums()
68 OS << " " << RegisterClasses[i]->getName() << "RegClassID"; in runEnums()
69 OS << " = " << i; in runEnums()
71 OS << "\n };\n"; in runEnums()
73 OS << "}\n"; in runEnums()
80 OS << "\n// Register alternate name indices\n"; in runEnums()
82 OS << "namespace " << Namespace << " {\n"; in runEnums()
83 OS << "enum {\n"; in runEnums()
85 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; in runEnums()
86 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; in runEnums()
87 OS << "};\n"; in runEnums()
89 OS << "}\n"; in runEnums()
93 OS << "} // End llvm namespace \n"; in runEnums()
94 OS << "#endif // GET_REGINFO_ENUM\n\n"; in runEnums()
98 RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS, in EmitRegMapping() argument
129 OS << " switch ("; in EmitRegMapping()
131 OS << "DwarfFlavour"; in EmitRegMapping()
133 OS << "EHFlavour"; in EmitRegMapping()
134 OS << ") {\n" in EmitRegMapping()
140 OS << " case " << i << ":\n"; in EmitRegMapping()
146 OS << " "; in EmitRegMapping()
148 OS << "RI->"; in EmitRegMapping()
149 OS << "mapDwarfRegToLLVMReg(" << DwarfRegNo << ", " in EmitRegMapping()
152 OS << "false"; in EmitRegMapping()
154 OS << "true"; in EmitRegMapping()
155 OS << " );\n"; in EmitRegMapping()
157 OS << " break;\n"; in EmitRegMapping()
159 OS << " }\n"; in EmitRegMapping()
175 OS << " switch ("; in EmitRegMapping()
177 OS << "DwarfFlavour"; in EmitRegMapping()
179 OS << "EHFlavour"; in EmitRegMapping()
180 OS << ") {\n" in EmitRegMapping()
186 OS << " case " << i << ":\n"; in EmitRegMapping()
191 OS << " "; in EmitRegMapping()
193 OS << "RI->"; in EmitRegMapping()
194 OS << "mapLLVMRegToDwarfReg(" << getQualifiedName(I->first) << ", " in EmitRegMapping()
197 OS << "false"; in EmitRegMapping()
199 OS << "true"; in EmitRegMapping()
200 OS << " );\n"; in EmitRegMapping()
202 OS << " break;\n"; in EmitRegMapping()
204 OS << " }\n"; in EmitRegMapping()
210 static void printBitVectorAsHex(raw_ostream &OS, in printBitVectorAsHex() argument
219 OS << format("0x%0*x, ", Digits, Value); in printBitVectorAsHex()
233 void print(raw_ostream &OS) { in print() argument
234 printBitVectorAsHex(OS, Values, 8); in print()
242 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, in runMCDesc() argument
244 EmitSourceFileHeader("MC Register Information", OS); in runMCDesc()
246 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; in runMCDesc()
247 OS << "#undef GET_REGINFO_MC_DESC\n"; in runMCDesc()
252 OS << "namespace llvm {\n\n"; in runMCDesc()
256 OS << "struct " << ClassName << " : public MCRegisterInfo {\n" in runMCDesc()
258 OS << "};\n"; in runMCDesc()
260 OS << "\nnamespace {\n"; in runMCDesc()
269 OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { " in runMCDesc()
274 OS << getQualifiedName((*I)->TheDef) << ", "; in runMCDesc()
275 OS << "0 };\n"; in runMCDesc()
279 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n"; in runMCDesc()
289 OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { "; in runMCDesc()
291 OS << getQualifiedName(SR[j]->TheDef) << ", "; in runMCDesc()
292 OS << "0 };\n"; in runMCDesc()
296 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n"; in runMCDesc()
304 OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { "; in runMCDesc()
306 OS << getQualifiedName(SR[j]->TheDef) << ", "; in runMCDesc()
307 OS << "0 };\n"; in runMCDesc()
309 OS << "}\n"; // End of anonymous namespace... in runMCDesc()
311 OS << "\nMCRegisterDesc " << TargetName in runMCDesc()
313 OS << " { \"NOREG\",\t0,\t0,\t0 },\n"; in runMCDesc()
319 OS << " { \""; in runMCDesc()
320 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t"; in runMCDesc()
322 OS << Reg.getName() << "_SubRegsSet,\t"; in runMCDesc()
324 OS << "Empty_SubRegsSet,\t"; in runMCDesc()
326 OS << Reg.getName() << "_SuperRegsSet"; in runMCDesc()
328 OS << "Empty_SuperRegsSet"; in runMCDesc()
329 OS << " },\n"; in runMCDesc()
331 OS << "};\n\n"; // End of register descriptors... in runMCDesc()
336 OS << "namespace { // Register classes...\n"; in runMCDesc()
347 OS << " // " << Name << " Register Class...\n" in runMCDesc()
352 OS << getQualifiedName(Reg) << ", "; in runMCDesc()
354 OS << "\n };\n\n"; in runMCDesc()
356 OS << " // " << Name << " Bit set.\n" in runMCDesc()
364 BVE.print(OS); in runMCDesc()
365 OS << "\n };\n\n"; in runMCDesc()
368 OS << "}\n\n"; in runMCDesc()
370 OS << "MCRegisterClass " << TargetName << "MCRegisterClasses[] = {\n"; in runMCDesc()
374 OS << " MCRegisterClass(" << RC.getQualifiedName() + "RegClassID" << ", " in runMCDesc()
386 OS << "};\n\n"; in runMCDesc()
389 OS << "static inline void Init" << TargetName in runMCDesc()
392 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " in runMCDesc()
396 EmitRegMapping(OS, Regs, false); in runMCDesc()
398 OS << "}\n\n"; in runMCDesc()
401 OS << "} // End llvm namespace \n"; in runMCDesc()
402 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; in runMCDesc()
406 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, in runTargetHeader() argument
408 EmitSourceFileHeader("Register Information Header Fragment", OS); in runTargetHeader()
410 OS << "\n#ifdef GET_REGINFO_HEADER\n"; in runTargetHeader()
411 OS << "#undef GET_REGINFO_HEADER\n"; in runTargetHeader()
416 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n"; in runTargetHeader()
417 OS << "#include <string>\n\n"; in runTargetHeader()
419 OS << "namespace llvm {\n\n"; in runTargetHeader()
421 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" in runTargetHeader()
435 OS << "\n// Subregister indices\n"; in runTargetHeader()
438 OS << "namespace " << Namespace << " {\n"; in runTargetHeader()
439 OS << "enum {\n NoSubRegister,\n"; in runTargetHeader()
441 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n"; in runTargetHeader()
442 OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n"; in runTargetHeader()
443 OS << "};\n"; in runTargetHeader()
445 OS << "}\n"; in runTargetHeader()
451 OS << "namespace " << RegisterClasses[0]->Namespace in runTargetHeader()
459 OS << " struct " << Name << "Class : public TargetRegisterClass {\n" in runTargetHeader()
462 OS << " ArrayRef<unsigned> " in runTargetHeader()
464 OS << " };\n"; in runTargetHeader()
467 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n"; in runTargetHeader()
469 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &" in runTargetHeader()
472 OS << "} // end of namespace " << TargetName << "\n\n"; in runTargetHeader()
474 OS << "} // End llvm namespace \n"; in runTargetHeader()
475 OS << "#endif // GET_REGINFO_HEADER\n\n"; in runTargetHeader()
482 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, in runTargetDesc() argument
484 EmitSourceFileHeader("Target Register and Register Classes Information", OS); in runTargetDesc()
486 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; in runTargetDesc()
487 OS << "#undef GET_REGINFO_TARGET_DESC\n"; in runTargetDesc()
489 OS << "namespace llvm {\n\n"; in runTargetDesc()
492 OS << "extern MCRegisterClass " << Target.getName() in runTargetDesc()
510 OS << "namespace { // Register classes...\n"; in runTargetDesc()
520 OS << " // " << Name in runTargetDesc()
525 OS << getEnumName(RC.VTs[i]) << ", "; in runTargetDesc()
526 OS << "MVT::Other\n };\n\n"; in runTargetDesc()
528 OS << "} // end anonymous namespace\n\n"; in runTargetDesc()
532 OS << "namespace " << RegisterClasses[0]->Namespace in runTargetDesc()
535 OS << " " << RegisterClasses[i]->getName() << "Class\t" in runTargetDesc()
540 OS << "\n static const TargetRegisterClass* const " in runTargetDesc()
566 OS << " // " << Name in runTargetDesc()
579 OS << ", "; in runTargetDesc()
580 OS << "&" << RC2.getQualifiedName() << "RegClass"; in runTargetDesc()
585 OS << (!Empty ? ", " : "") << "NULL"; in runTargetDesc()
586 OS << "\n };\n\n"; in runTargetDesc()
597 OS << " static const unsigned " << Name << "SubclassMask[] = { "; in runTargetDesc()
598 printBitVectorAsHex(OS, RC.getSubClasses(), 32); in runTargetDesc()
599 OS << "};\n\n"; in runTargetDesc()
611 OS << " static const TargetRegisterClass* const " in runTargetDesc()
614 OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n"; in runTargetDesc()
615 OS << " NULL\n };\n\n"; in runTargetDesc()
621 OS << RC.getName() << "Class::" << RC.getName() in runTargetDesc()
628 OS << "NullRegClasses, "; in runTargetDesc()
630 OS << RC.getName() + "Superclasses, "; in runTargetDesc()
631 OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null")) in runTargetDesc()
635 OS << "\nstatic inline unsigned " << RC.getName() in runTargetDesc()
642 OS << " static const unsigned AltOrder" << oi << "[] = {"; in runTargetDesc()
644 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); in runTargetDesc()
645 OS << " };\n"; in runTargetDesc()
647 OS << " const MCRegisterClass &MCR = " << Target.getName() in runTargetDesc()
652 OS << "),\n makeArrayRef(AltOrder" << oi; in runTargetDesc()
653 OS << ")\n };\n const unsigned Select = " << RC.getName() in runTargetDesc()
659 OS << "}\n"; in runTargetDesc()
662 OS << "\nnamespace {\n"; in runTargetDesc()
663 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; in runTargetDesc()
665 OS << " &" << RegisterClasses[i]->getQualifiedName() in runTargetDesc()
667 OS << " };\n"; in runTargetDesc()
668 OS << "}\n"; // End of anonymous namespace... in runTargetDesc()
672 OS << "\n static const TargetRegisterInfoDesc " in runTargetDesc()
675 OS << " { 0, 0 },\n"; in runTargetDesc()
680 OS << " { "; in runTargetDesc()
681 OS << Reg.CostPerUse << ", " in runTargetDesc()
684 OS << " };\n"; // End of register descriptors... in runTargetDesc()
693 OS << "\n static const char *const " << TargetName in runTargetDesc()
696 OS << SubRegIndices[i]->getName(); in runTargetDesc()
698 OS << "\", \""; in runTargetDesc()
700 OS << "\" };\n\n"; in runTargetDesc()
704 OS << " enum {"; in runTargetDesc()
706 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1; in runTargetDesc()
708 OS << ','; in runTargetDesc()
710 OS << "\n };\n\n"; in runTargetDesc()
712 OS << "\n"; in runTargetDesc()
718 OS << "unsigned " << ClassName in runTargetDesc()
726 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n"; in runTargetDesc()
727 OS << " switch (Index) {\n"; in runTargetDesc()
728 OS << " default: return 0;\n"; in runTargetDesc()
731 OS << " case " << getQualifiedName(ii->first) in runTargetDesc()
733 OS << " };\n" << " break;\n"; in runTargetDesc()
735 OS << " };\n"; in runTargetDesc()
736 OS << " return 0;\n"; in runTargetDesc()
737 OS << "}\n\n"; in runTargetDesc()
739 OS << "unsigned " << ClassName in runTargetDesc()
747 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n"; in runTargetDesc()
750 OS << " if (SubRegNo == " << getQualifiedName(ii->second->TheDef) in runTargetDesc()
752 OS << " return 0;\n"; in runTargetDesc()
754 OS << " };\n"; in runTargetDesc()
755 OS << " return 0;\n"; in runTargetDesc()
756 OS << "}\n\n"; in runTargetDesc()
759 OS << "unsigned " << ClassName in runTargetDesc()
769 OS << " case " << getQualifiedName(SubRegIndices[i]) in runTargetDesc()
773 OS << " case " << getQualifiedName(SubRegIndices[j]) in runTargetDesc()
778 OS << " }\n"; in runTargetDesc()
780 OS << " }\n}\n\n"; in runTargetDesc()
783 OS << "const TargetRegisterClass *" << ClassName in runTargetDesc()
787 OS << " assert(Idx == 0 && \"Target has no sub-registers\");\n" in runTargetDesc()
793 OS << " static const uint8_t Table["; in runTargetDesc()
795 OS << " static const uint16_t Table["; in runTargetDesc()
798 OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n"; in runTargetDesc()
801 OS << " {\t// " << RC.getName() << "\n"; in runTargetDesc()
805 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName() in runTargetDesc()
808 OS << " 0,\t// " << Idx->getName() << "\n"; in runTargetDesc()
810 OS << " },\n"; in runTargetDesc()
812 OS << " };\n assert(RC && \"Missing regclass\");\n" in runTargetDesc()
818 OS << "}\n\n"; in runTargetDesc()
821 OS << "extern MCRegisterDesc " << TargetName << "RegDesc[];\n"; in runTargetDesc()
823 OS << ClassName << "::" << ClassName in runTargetDesc()
832 EmitRegMapping(OS, Regs, true); in runTargetDesc()
834 OS << "}\n\n"; in runTargetDesc()
836 OS << "} // End llvm namespace \n"; in runTargetDesc()
837 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; in runTargetDesc()
840 void RegisterInfoEmitter::run(raw_ostream &OS) { in run() argument
845 runEnums(OS, Target, RegBank); in run()
846 runMCDesc(OS, Target, RegBank); in run()
847 runTargetHeader(OS, Target, RegBank); in run()
848 runTargetDesc(OS, Target, RegBank); in run()