Lines Matching refs:stores

36 pair of volatile stores. On the other hand, a non-volatile non-atomic load can
54 because any optimization dealing with stores needs to be aware of it.
99 For cases where simple loads and stores are not sufficient, LLVM provides
104 non-atomic loads and stores, but provide additional guarantees in situations
150   The rule is essentially that all memory accessed with basic loads and stores
154   variable.  Note that NotAtomic volatile loads and stores are not properly
161   otherwise exist is allowed; introducing stores to shared variables is not. See
167   unaligned stores: it is not allowed in general to convert an unaligned store
168   into two aligned stores of the same width as the unaligned store. Backends are
194   stores.)
198   single load into multiple loads, transforms a store into multiple stores,
199   narrows a store, or stores a value which would not be stored otherwise.  Some
201   rematerializing a load, and turning loads and stores into a memcpy
208   unordered loads and unordered stores, a load cannot see a value which was
243   stores.  No fences are required.  ``cmpxchg`` and ``atomicrmw`` are required
250 other memory with normal loads and stores.
263   also possible to move stores from before an Acquire load or read-modify-write
293   operation to before it, and move non-Release stores from after an Release
328 and Release semantics for stores. Additionally, it guarantees that a total
342   SequentiallyConsistent loads and stores, the same reorderings are allowed as
343   for Acquire loads and Release stores, except that SequentiallyConsistent
348   operations and SequentiallyConsistent stores require Release
350   SequentiallyConsistent stores followed by SequentiallyConsistent loads. This
352   fence after the stores; which is preferred varies by architecture.
387   memcpy/memset, including unordered loads/stores.  It can pull operations
390 * LICM: Unordered loads/stores can be moved out of a loop.  It just treats
394 * DSE: Unordered stores can be DSE'ed like normal stores.  Monotonic stores can
402   atomic loads and stores.
434 On x86, all atomic loads generate a ``MOV``. SequentiallyConsistent stores
435 generate an ``XCHG``, other stores generate a ``MOV``. SequentiallyConsistent
445 operation. Loads and stores generate normal instructions.  ``cmpxchg`` and
456 * large loads/stores -> ll-sc/cmpxchg
600 architectures support atomic loads and stores directly (possibly by emitting a