Lines Matching refs:Cond
143 IValueT encodeCondition(CondARM32::Cond Cond) { in encodeCondition() argument
144 return static_cast<IValueT>(Cond); in encodeCondition()
794 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT InstType, in emitType01() argument
806 assert(CondARM32::isDefined(Cond)); in emitType01()
807 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | in emitType01()
814 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT Opcode, in emitType01() argument
820 emitType01(Cond, Opcode, Rd, Rn, OpSrc1, SetFlags, RuleChecks, InstName); in emitType01()
823 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT Opcode, in emitType01() argument
842 emitType01(Cond, kInstTypeDataRegister, Opcode, SetFlags, Rn, Rd, Src1Value, in emitType01()
848 emitType01(Cond, kInstTypeDataRegister, Opcode, SetFlags, Rn, Rd, Src1Value, in emitType01()
868 emitType01(Cond, kInstTypeDataImmediate, Opcode, SetFlags, Rn, Rd, in emitType01()
879 emitType01(Cond, kInstTypeDataRegShift, Opcode, SetFlags, Rn, Rd, Src1Value, in emitType01()
886 void AssemblerARM32::emitType05(CondARM32::Cond Cond, IOffsetT Offset, in emitType05() argument
891 assert(CondARM32::isDefined(Cond)); in emitType05()
892 IValueT Encoding = static_cast<int32_t>(Cond) << kConditionShift | in emitType05()
898 void AssemblerARM32::emitBranch(Label *L, CondARM32::Cond Cond, bool Link) { in emitBranch() argument
902 emitType05(Cond, Dest, Link); in emitBranch()
907 emitType05(Cond, L->getEncodedPosition(), Link); in emitBranch()
911 void AssemblerARM32::emitCompareOp(CondARM32::Cond Cond, IValueT Opcode, in emitCompareOp() argument
930 emitType01(Cond, Opcode, Rd, Rn, OpSrc1, SetFlags, NoChecks, InstName); in emitCompareOp()
933 void AssemblerARM32::emitMemOp(CondARM32::Cond Cond, IValueT InstType, in emitMemOp() argument
937 assert(CondARM32::isDefined(Cond)); in emitMemOp()
938 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | in emitMemOp()
944 void AssemblerARM32::emitMemOp(CondARM32::Cond Cond, bool IsLoad, bool IsByte, in emitMemOp() argument
972 emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address); in emitMemOp()
995 emitMemOp(Cond, kInstTypeRegisterShift, IsLoad, IsByte, Rt, Address); in emitMemOp()
1001 void AssemblerARM32::emitMemOpEnc3(CondARM32::Cond Cond, IValueT Opcode, in emitMemOpEnc3() argument
1020 assert(CondARM32::isDefined(Cond)); in emitMemOpEnc3()
1025 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | in emitMemOpEnc3()
1039 assert(CondARM32::isDefined(Cond)); in emitMemOpEnc3()
1052 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | in emitMemOpEnc3()
1060 void AssemblerARM32::emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, in emitDivOp() argument
1065 assert(CondARM32::isDefined(Cond)); in emitDivOp()
1066 const IValueT Encoding = Opcode | (encodeCondition(Cond) << kConditionShift) | in emitDivOp()
1073 void AssemblerARM32::emitInsertExtractInt(CondARM32::Cond Cond, in emitInsertExtractInt() argument
1081 assert(CondARM32::isDefined(Cond)); in emitInsertExtractInt()
1109 (encodeCondition(Cond) << kConditionShift) | in emitInsertExtractInt()
1117 void AssemblerARM32::emitMoveSS(CondARM32::Cond Cond, IValueT Sd, IValueT Sm) { in emitMoveSS() argument
1124 emitVFPsss(Cond, VmovssOpcode, Sd, S0, Sm); in emitMoveSS()
1127 void AssemblerARM32::emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, in emitMulOp() argument
1134 assert(CondARM32::isDefined(Cond)); in emitMulOp()
1135 IValueT Encoding = Opcode | (encodeCondition(Cond) << kConditionShift) | in emitMulOp()
1142 void AssemblerARM32::emitMultiMemOp(CondARM32::Cond Cond, in emitMultiMemOp() argument
1145 assert(CondARM32::isDefined(Cond)); in emitMultiMemOp()
1148 IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 | in emitMultiMemOp()
1154 void AssemblerARM32::emitSignExtend(CondARM32::Cond Cond, IValueT Opcode, in emitSignExtend() argument
1189 assert(CondARM32::isDefined(Cond)); in emitSignExtend()
1194 IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | Opcode | in emitSignExtend()
1268 void AssemblerARM32::emitVFPddd(CondARM32::Cond Cond, IValueT Opcode, in emitVFPddd() argument
1273 assert(CondARM32::isDefined(Cond)); in emitVFPddd()
1276 Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) | in emitVFPddd()
1283 void AssemblerARM32::emitVFPddd(CondARM32::Cond Cond, IValueT Opcode, in emitVFPddd() argument
1289 emitVFPddd(Cond, Opcode, Dd, Dn, Dm); in emitVFPddd()
1292 void AssemblerARM32::emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, in emitVFPsss() argument
1297 assert(CondARM32::isDefined(Cond)); in emitVFPsss()
1300 Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) | in emitVFPsss()
1307 void AssemblerARM32::emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, in emitVFPsss() argument
1313 emitVFPsss(Cond, Opcode, Sd, Sn, Sm); in emitVFPsss()
1318 CondARM32::Cond Cond) { in adc() argument
1332 emitType01(Cond, AdcOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in adc()
1338 CondARM32::Cond Cond) { in add() argument
1356 emitType01(Cond, Add, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in add()
1362 CondARM32::Cond Cond) { in and_() argument
1376 emitType01(Cond, And, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in and_()
1380 void AssemblerARM32::b(Label *L, CondARM32::Cond Cond) { in b() argument
1381 emitBranch(L, Cond, false); in b()
1396 CondARM32::Cond Cond) { in bic() argument
1410 emitType01(Cond, BicOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in bic()
1421 constexpr CondARM32::Cond Cond = CondARM32::AL; in bl() local
1424 emitType05(Cond, Immed, Link); in bl()
1436 constexpr CondARM32::Cond Cond = CondARM32::AL; in blx() local
1437 int32_t Encoding = (encodeCondition(Cond) << kConditionShift) | B24 | B21 | in blx()
1442 void AssemblerARM32::bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond) { in bx() argument
1447 assert(CondARM32::isDefined(Cond)); in bx()
1448 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B24 | in bx()
1455 CondARM32::Cond Cond) { in clz() argument
1469 assert(CondARM32::isDefined(Cond)); in clz()
1472 const IValueT Encoding = PredefinedBits | (Cond << kConditionShift) | in clz()
1478 CondARM32::Cond Cond) { in cmn() argument
1492 emitCompareOp(Cond, CmnOpcode, OpRn, OpSrc1, CmnName); in cmn()
1496 CondARM32::Cond Cond) { in cmp() argument
1510 emitCompareOp(Cond, CmpOpcode, OpRn, OpSrc1, CmpName); in cmp()
1528 CondARM32::Cond Cond) { in eor() argument
1542 emitType01(Cond, EorOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in eor()
1547 CondARM32::Cond Cond, const TargetInfo &TInfo) { in ldr() argument
1580 emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, LdrName); in ldr()
1593 emitMemOpEnc3(Cond, L | B7 | B5 | B4, Rt, OpAddress, TInfo, Ldrh); in ldr()
1612 emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, LdrName); in ldr()
1618 void AssemblerARM32::emitMemExOp(CondARM32::Cond Cond, Type Ty, bool IsLoad, in emitMemExOp() argument
1649 assert(CondARM32::isDefined(Cond)); in emitMemExOp()
1650 IValueT Encoding = (Cond << kConditionShift) | B24 | B23 | B11 | B10 | B9 | in emitMemExOp()
1658 CondARM32::Cond Cond, const TargetInfo &TInfo) { in ldrex() argument
1682 emitMemExOp(Cond, Ty, IsLoad, OpRt, Rm, OpAddress, TInfo, LdrexName); in ldrex()
1685 void AssemblerARM32::emitShift(const CondARM32::Cond Cond, in emitShift() argument
1706 emitType01(Cond, kInstTypeDataRegShift, ShiftOpcode, SetFlags, Rn, Rd, in emitShift()
1721 emitType01(Cond, kInstTypeDataRegShift, ShiftOpcode, SetFlags, Rn, Rd, in emitShift()
1730 CondARM32::Cond Cond) { in asr() argument
1732 emitShift(Cond, OperandARM32::ASR, OpRd, OpRm, OpSrc1, SetFlags, AsrName); in asr()
1737 CondARM32::Cond Cond) { in lsl() argument
1739 emitShift(Cond, OperandARM32::LSL, OpRd, OpRm, OpSrc1, SetFlags, LslName); in lsl()
1744 CondARM32::Cond Cond) { in lsr() argument
1746 emitShift(Cond, OperandARM32::LSR, OpRd, OpRm, OpSrc1, SetFlags, LsrName); in lsr()
1750 CondARM32::Cond Cond) { in mov() argument
1768 emitType01(Cond, MovOpcode, Rd, Rn, OpSrc, SetFlags, RdIsPcAndSetFlags, in mov()
1772 void AssemblerARM32::emitMovwt(CondARM32::Cond Cond, bool IsMovW, in emitMovwt() argument
1786 assert(CondARM32::isDefined(Cond)); in emitMovwt()
1789 const IValueT Encoding = encodeCondition(Cond) << kConditionShift | Opcode | in emitMovwt()
1796 CondARM32::Cond Cond) { in movw() argument
1804 emitMovwt(Cond, IsMovW, OpRd, OpSrc, MovwName); in movw()
1808 CondARM32::Cond Cond) { in movt() argument
1816 emitMovwt(Cond, IsMovW, OpRd, OpSrc, MovtName); in movt()
1820 CondARM32::Cond Cond) { in mvn() argument
1837 emitType01(Cond, MvnOpcode, Rd, Rn, OpSrc, SetFlags, RdIsPcAndSetFlags, in mvn()
1846 constexpr CondARM32::Cond Cond = CondARM32::AL; in nop() local
1847 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B25 | in nop()
1854 CondARM32::Cond Cond) { in sbc() argument
1868 emitType01(Cond, SbcOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in sbc()
1873 const Operand *OpSrc1, CondARM32::Cond Cond) { in sdiv() argument
1888 emitDivOp(Cond, SdivOpcode, Rd, Rn, Rm); in sdiv()
1892 CondARM32::Cond Cond, const TargetInfo &TInfo) { in str() argument
1917 emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, StrName); in str()
1930 emitMemOpEnc3(Cond, B7 | B5 | B4, Rt, OpAddress, TInfo, Strh); in str()
1945 emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, StrName); in str()
1952 const Operand *OpAddress, CondARM32::Cond Cond, in strex() argument
1982 emitMemExOp(Cond, Ty, !IsLoad, OpRd, Rt, OpAddress, TInfo, StrexName); in strex()
1987 CondARM32::Cond Cond) { in orr() argument
2001 emitType01(Cond, OrrOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in orr()
2005 void AssemblerARM32::pop(const Variable *OpRt, CondARM32::Cond Cond) { in pop() argument
2021 emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address); in pop()
2024 void AssemblerARM32::popList(const IValueT Registers, CondARM32::Cond Cond) { in popList() argument
2031 emitMultiMemOp(Cond, IA_W, IsLoad, RegARM32::Encoded_Reg_sp, Registers); in popList()
2034 void AssemblerARM32::push(const Operand *OpRt, CondARM32::Cond Cond) { in push() argument
2050 emitMemOp(Cond, kInstTypeMemImmediate, isLoad, isByte, Rt, Address); in push()
2053 void AssemblerARM32::pushList(const IValueT Registers, CondARM32::Cond Cond) { in pushList() argument
2060 emitMultiMemOp(Cond, DB_W, IsLoad, RegARM32::Encoded_Reg_sp, Registers); in pushList()
2065 CondARM32::Cond Cond) { in mla() argument
2083 emitMulOp(Cond, MlaOpcode, Ra, Rd, Rn, Rm, !SetFlags); in mla()
2088 CondARM32::Cond Cond) { in mls() argument
2101 emitMulOp(Cond, MlsOpcode, Ra, Rd, Rn, Rm, !SetFlags); in mls()
2106 CondARM32::Cond Cond) { in mul() argument
2121 emitMulOp(Cond, MulOpcode, RegARM32::Encoded_Reg_r0, Rd, Rn, Rm, SetFlags); in mul()
2124 void AssemblerARM32::emitRdRm(CondARM32::Cond Cond, IValueT Opcode, in emitRdRm() argument
2130 (Cond << kConditionShift) | Opcode | (Rd << kRdShift) | (Rm << kRmShift); in emitRdRm()
2135 CondARM32::Cond Cond) { in rbit() argument
2143 emitRdRm(Cond, RbitOpcode, OpRd, OpRm, RbitName); in rbit()
2147 CondARM32::Cond Cond) { in rev() argument
2155 emitRdRm(Cond, RevOpcode, OpRd, OpRm, RevName); in rev()
2160 CondARM32::Cond Cond) { in rsb() argument
2174 emitType01(Cond, RsbOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in rsb()
2180 CondARM32::Cond Cond) { in rsc() argument
2200 emitType01(Cond, RscOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in rsc()
2205 CondARM32::Cond Cond) { in sxt() argument
2208 emitSignExtend(Cond, SxtOpcode, OpRd, OpSrc0, SxtName); in sxt()
2213 CondARM32::Cond Cond) { in sub() argument
2231 emitType01(Cond, SubOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in sub()
2257 CondARM32::Cond Cond) { in tst() argument
2271 emitCompareOp(Cond, TstOpcode, OpRn, OpSrc1, TstName); in tst()
2275 const Operand *OpSrc1, CondARM32::Cond Cond) { in udiv() argument
2290 emitDivOp(Cond, UdivOpcode, Rd, Rn, Rm); in udiv()
2295 CondARM32::Cond Cond) { in umull() argument
2313 emitMulOp(Cond, UmullOpcode, RdLo, RdHi, Rn, Rm, SetFlags); in umull()
2317 CondARM32::Cond Cond) { in uxt() argument
2320 emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName); in uxt()
2324 CondARM32::Cond Cond) { in vabss() argument
2334 emitVFPsss(Cond, VabssOpcode, Sd, S0, Sm); in vabss()
2338 CondARM32::Cond Cond) { in vabsd() argument
2348 emitVFPddd(Cond, VabsdOpcode, Dd, D0, Dm); in vabsd()
2370 const Operand *OpSm, CondARM32::Cond Cond) { in vadds() argument
2378 emitVFPsss(Cond, VaddsOpcode, OpSd, OpSn, OpSm, Vadds); in vadds()
2409 const Operand *OpDm, CondARM32::Cond Cond) { in vaddd() argument
2417 emitVFPddd(Cond, VadddOpcode, OpDd, OpDn, OpDm, Vaddd); in vaddd()
2541 CondARM32::Cond Cond) { in vcmpd() argument
2547 emitVFPddd(Cond, VcmpdOpcode, Dd, Dn, Dm); in vcmpd()
2550 void AssemblerARM32::vcmpdz(const Operand *OpDd, CondARM32::Cond Cond) { in vcmpdz() argument
2556 emitVFPddd(Cond, VcmpdzOpcode, Dd, Dn, Dm); in vcmpdz()
2560 CondARM32::Cond Cond) { in vcmps() argument
2566 emitVFPsss(Cond, VcmpsOpcode, Sd, Sn, Sm); in vcmps()
2569 void AssemblerARM32::vcmpsz(const Operand *OpSd, CondARM32::Cond Cond) { in vcmpsz() argument
2575 emitVFPsss(Cond, VcmpszOpcode, Sd, Sn, Sm); in vcmpsz()
2578 void AssemblerARM32::emitVFPsd(CondARM32::Cond Cond, IValueT Opcode, IValueT Sd, in emitVFPsd() argument
2582 assert(CondARM32::isDefined(Cond)); in emitVFPsd()
2585 Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) | in emitVFPsd()
2592 CondARM32::Cond Cond) { in vcvtdi() argument
2602 emitVFPds(Cond, VcvtdiOpcode, Dd, Sm); in vcvtdi()
2606 CondARM32::Cond Cond) { in vcvtdu() argument
2616 emitVFPds(Cond, VcvtduOpcode, Dd, Sm); in vcvtdu()
2620 CondARM32::Cond Cond) { in vcvtsd() argument
2626 emitVFPsd(Cond, VcvtsdOpcode, Sd, Dm); in vcvtsd()
2630 CondARM32::Cond Cond) { in vcvtis() argument
2641 emitVFPsss(Cond, VcvtisOpcode, Sd, S0, Sm); in vcvtis()
2645 CondARM32::Cond Cond) { in vcvtid() argument
2656 emitVFPsd(Cond, VcvtidOpcode, Sd, Dm); in vcvtid()
2660 CondARM32::Cond Cond) { in vcvtsi() argument
2671 emitVFPsss(Cond, VcvtsiOpcode, Sd, S0, Sm); in vcvtsi()
2675 CondARM32::Cond Cond) { in vcvtsu() argument
2686 emitVFPsss(Cond, VcvtsuOpcode, Sd, S0, Sm); in vcvtsu()
2690 CondARM32::Cond Cond) { in vcvtud() argument
2700 emitVFPsd(Cond, VcvtudOpcode, Sd, Dm); in vcvtud()
2704 CondARM32::Cond Cond) { in vcvtus() argument
2715 emitVFPsss(Cond, VcvtsiOpcode, Sd, S0, Sm); in vcvtus()
2762 void AssemblerARM32::emitVFPds(CondARM32::Cond Cond, IValueT Opcode, IValueT Dd, in emitVFPds() argument
2766 assert(CondARM32::isDefined(Cond)); in emitVFPds()
2769 Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) | in emitVFPds()
2776 CondARM32::Cond Cond) { in vcvtds() argument
2781 emitVFPds(Cond, VcvtdsOpcode, Dd, Sm); in vcvtds()
2785 const Operand *OpSm, CondARM32::Cond Cond) { in vdivs() argument
2793 emitVFPsss(Cond, VdivsOpcode, OpSd, OpSn, OpSm, Vdivs); in vdivs()
2797 const Operand *OpDm, CondARM32::Cond Cond) { in vdivd() argument
2805 emitVFPddd(Cond, VdivdOpcode, OpDd, OpDn, OpDm, Vdivd); in vdivd()
2820 (encodeCondition(CondARM32::Cond::kNone) << kConditionShift) | in veord()
2839 CondARM32::Cond Cond, const TargetInfo &TInfo) { in vldrd() argument
2847 assert(CondARM32::isDefined(Cond)); in vldrd()
2854 (encodeCondition(Cond) << kConditionShift) | in vldrd()
2861 CondARM32::Cond Cond, const TargetInfo &TInfo) { in vldrq() argument
2872 assert(CondARM32::isDefined(Cond)); in vldrq()
2879 (encodeCondition(Cond) << kConditionShift) | in vldrq()
2886 CondARM32::Cond Cond, const TargetInfo &TInfo) { in vldrs() argument
2894 assert(CondARM32::isDefined(Cond)); in vldrs()
2901 (encodeCondition(Cond) << kConditionShift) | in vldrs()
3056 CondARM32::Cond Cond) { in vmovd() argument
3068 emitVFPddd(Cond, OpcodePlusImm8, Dd, D0, D0); in vmovd()
3072 CondARM32::Cond Cond) { in vmovdd() argument
3082 emitVFPddd(Cond, VmovddOpcode, Dd, D0, Dm); in vmovdd()
3086 const Operand *OpRt2, CondARM32::Cond Cond) { in vmovdrr() argument
3102 assert(CondARM32::isDefined(Cond)); in vmovdrr()
3104 (encodeCondition(Cond) << kConditionShift) | (Rt2 << 16) | in vmovdrr()
3111 const Operand *OpRt, CondARM32::Cond Cond) { in vmovqir() argument
3116 emitInsertExtractInt(Cond, OpQn, Index, OpRt, !IsExtract, Vmovdr); in vmovqir()
3120 const Operand *OpSm, CondARM32::Cond Cond) { in vmovqis() argument
3125 emitMoveSS(Cond, Sd, Sm); in vmovqis()
3129 uint32_t Index, CondARM32::Cond Cond) { in vmovrqi() argument
3134 emitInsertExtractInt(Cond, OpQn, Index, OpRt, IsExtract, Vmovrd); in vmovrqi()
3138 const Operand *OpDm, CondARM32::Cond Cond) { in vmovrrd() argument
3154 assert(CondARM32::isDefined(Cond)); in vmovrrd()
3156 (encodeCondition(Cond) << kConditionShift) | (Rt2 << 16) | in vmovrrd()
3163 CondARM32::Cond Cond) { in vmovrs() argument
3173 assert(CondARM32::isDefined(Cond)); in vmovrs()
3174 IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 | B26 | in vmovrs()
3182 CondARM32::Cond Cond) { in vmovs() argument
3194 emitVFPsss(Cond, OpcodePlusImm8, Sd, S0, S0); in vmovs()
3198 CondARM32::Cond Cond) { in vmovss() argument
3202 emitMoveSS(Cond, Sd, Sm); in vmovss()
3206 uint32_t Index, CondARM32::Cond Cond) { in vmovsqi() argument
3212 emitMoveSS(Cond, Sd, Sm); in vmovsqi()
3216 CondARM32::Cond Cond) { in vmovsr() argument
3228 assert(CondARM32::isDefined(Cond)); in vmovsr()
3229 IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 | B26 | in vmovsr()
3236 const Operand *OpDm, CondARM32::Cond Cond) { in vmlad() argument
3244 emitVFPddd(Cond, VmladOpcode, OpDd, OpDn, OpDm, Vmlad); in vmlad()
3248 const Operand *OpSm, CondARM32::Cond Cond) { in vmlas() argument
3256 emitVFPsss(Cond, VmlasOpcode, OpSd, OpSn, OpSm, Vmlas); in vmlas()
3260 const Operand *OpDm, CondARM32::Cond Cond) { in vmlsd() argument
3268 emitVFPddd(Cond, VmladOpcode, OpDd, OpDn, OpDm, Vmlad); in vmlsd()
3272 const Operand *OpSm, CondARM32::Cond Cond) { in vmlss() argument
3280 emitVFPsss(Cond, VmlasOpcode, OpSd, OpSn, OpSm, Vmlas); in vmlss()
3283 void AssemblerARM32::vmrsAPSR_nzcv(CondARM32::Cond Cond) { in vmrsAPSR_nzcv() argument
3289 assert(CondARM32::isDefined(Cond)); in vmrsAPSR_nzcv()
3292 (encodeCondition(Cond) << kConditionShift); in vmrsAPSR_nzcv()
3297 const Operand *OpSm, CondARM32::Cond Cond) { in vmuls() argument
3305 emitVFPsss(Cond, VmulsOpcode, OpSd, OpSn, OpSm, Vmuls); in vmuls()
3309 const Operand *OpDm, CondARM32::Cond Cond) { in vmuld() argument
3317 emitVFPddd(Cond, VmuldOpcode, OpDd, OpDn, OpDm, Vmuld); in vmuld()
3683 CondARM32::Cond Cond, const TargetInfo &TInfo) { in vstrd() argument
3691 assert(CondARM32::isDefined(Cond)); in vstrd()
3698 (encodeCondition(Cond) << kConditionShift) | in vstrd()
3705 CondARM32::Cond Cond, const TargetInfo &TInfo) { in vstrq() argument
3716 assert(CondARM32::isDefined(Cond)); in vstrq()
3723 (encodeCondition(Cond) << kConditionShift) | in vstrq()
3730 CondARM32::Cond Cond, const TargetInfo &TInfo) { in vstrs() argument
3738 assert(CondARM32::isDefined(Cond)); in vstrs()
3745 B27 | B26 | B24 | B11 | B9 | (encodeCondition(Cond) << kConditionShift) | in vstrs()
3804 const Operand *OpSm, CondARM32::Cond Cond) { in vsubs() argument
3812 emitVFPsss(Cond, VsubsOpcode, OpSd, OpSn, OpSm, Vsubs); in vsubs()
3816 const Operand *OpDm, CondARM32::Cond Cond) { in vsubd() argument
3824 emitVFPddd(Cond, VsubdOpcode, OpDd, OpDn, OpDm, Vsubd); in vsubd()
3962 void AssemblerARM32::emitVStackOp(CondARM32::Cond Cond, IValueT Opcode, in emitVStackOp() argument
3972 assert(CondARM32::isDefined(Cond)); in emitVStackOp()
3973 const IValueT Encoding = Opcode | (Cond << kConditionShift) | DLastBit | in emitVStackOp()
3979 CondARM32::Cond Cond) { in vpop() argument
3990 emitVStackOp(Cond, VpopOpcode, OpBaseReg, NumConsecRegs); in vpop()
3994 CondARM32::Cond Cond) { in vpush() argument
4005 emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs); in vpush()
4070 CondARM32::Cond Cond) { in vsqrtd() argument
4080 emitVFPddd(Cond, VsqrtdOpcode, Dd, D0, Dm); in vsqrtd()
4084 CondARM32::Cond Cond) { in vsqrts() argument
4094 emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm); in vsqrts()