1078   IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", InstName));  in emitInsertExtractInt()  local
1092     Dn = Dn | mask(Index, 3, 1);  in emitInsertExtractInt()
1098     Dn = Dn | mask(Index, 2, 1);  in emitInsertExtractInt()
1104     Dn = Dn | mask(Index, 1, 1);  in emitInsertExtractInt()
1111                            (getXXXXInRegYXXXX(Dn) << kRnShift) | (Rt << 12) |  in emitInsertExtractInt()
1113                            (getYInRegYXXXX(Dn) << 7) | (Opcode2 << 5);  in emitInsertExtractInt()
1200 void AssemblerARM32::emitSIMDBase(IValueT Opcode, IValueT Dd, IValueT Dn,  in emitSIMDBase()  argument
1204       (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) |  in emitSIMDBase()
1206       (getYInRegYXXXX(Dn) << 7) | (encodeBool(UseQRegs) << 6) |  in emitSIMDBase()
1212                               IValueT Dn, IValueT Dm, bool UseQRegs) {  in emitSIMD()  argument
1216   emitSIMDBase(Opcode | (ElmtSize << ElmtShift), Dd, Dn, Dm, UseQRegs,  in emitSIMD()
1269                                 IValueT Dd, IValueT Dn, IValueT Dm) {  in emitVFPddd()  argument
1271   assert(Dn < RegARM32::getNumDRegs());  in emitVFPddd()
1277       (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) |  in emitVFPddd()
1278       (getXXXXInRegYXXXX(Dd) << 12) | (getYInRegYXXXX(Dn) << 7) |  in emitVFPddd()
1287   IValueT Dn = encodeDRegister(OpDn, "Dn", InstName);  in emitVFPddd()  local
1289   emitVFPddd(Cond, Opcode, Dd, Dn, Dm);  in emitVFPddd()
2362   constexpr IValueT Dn = 0;  in vabsq()  local
2366   emitSIMDBase(VabsqOpcode, Dd, Dn, Dm, UseQRegs, isFloatingType(ElmtTy));  in vabsq()
2546   constexpr IValueT Dn = 0;  in vcmpd()  local
2547   emitVFPddd(Cond, VcmpdOpcode, Dd, Dn, Dm);  in vcmpd()
2554   constexpr IValueT Dn = 0;  in vcmpdz()  local
2556   emitVFPddd(Cond, VcmpdzOpcode, Dd, Dn, Dm);  in vcmpdz()
2816   IValueT Dn = encodeDRegister(OpDn, "Dn", Veord);  in veord()  local
2821       (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) |  in veord()
2822       (getXXXXInRegYXXXX(Dd) << 12) | (getYInRegYXXXX(Dn) << 7) |  in veord()
3362   const IValueT Dn = mapQRegToDReg(Qn);  in vmulh()  local
3367   emitSIMDBase(VmullOpcode | (ElmtSize << ElmtShift), Dd, Dn, Dm, UseQRegs,  in vmulh()
3402   const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vmull));  in vmlap()  local
3407   emitSIMDBase(VmullOpcode | (ElmtSize << ElmtShift), Dd, Dn, Dm, UseQRegs,  in vmlap()
3433   const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vdup));  in vdup()  local
3462   emitSIMDBase(VdupOpcode, Dd, Imm4, Dn + (Lower ? 0 : 1), UseQRegs, IsFloatTy);  in vdup()
3479   const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vzip));  in vzip()  local
3493   if (Dd != Dn)  in vzip()
3494     emitSIMDBase(VmovOpcode, Dd, Dn, Dn, UseQRegs, IsFloatTy);  in vzip()
3554   const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vmov));  in vmovlq()  local
3564   if (Dd + 1 != Dn + 1)  in vmovlq()
3565     emitSIMDBase(VmovOpcode, Dd + 1, Dn + 1, Dn + 1, UseQRegs, IsFloat);  in vmovlq()
3580   const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vmov));  in vmovhq()  local
3588   if (Dd != Dn)  in vmovhq()
3589     emitSIMDBase(VmovOpcode, Dd, Dn, Dn, UseQRegs, IsFloat);  in vmovhq()
3606   const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vmov));  in vmovhlq()  local
3616   if (Dd + 1 != Dn + 1)  in vmovhlq()
3617     emitSIMDBase(VmovOpcode, Dd + 1, Dn + 1, Dn + 1, UseQRegs, IsFloat);  in vmovhlq()
3632   const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vmov));  in vmovlhq()  local
3642   if (Dd != Dn)  in vmovlhq()
3643     emitSIMDBase(VmovOpcode, Dd, Dn, Dn, UseQRegs, IsFloat);  in vmovlhq()
3920   const IValueT Dn = mapQRegToDReg(Qn);  in vqmovn2()  local
3930     emitSIMDBase(VqmovnOpcode, Dd + 1, 0, Dn, UseQRegs, IsFloatTy);  in vqmovn2()
3937     emitSIMDBase(VqmovnOpcode, Dd + 1, 0, Dn, UseQRegs, IsFloatTy);  in vqmovn2()