Lines Matching refs:ElmtTy
219 bool encodeAdvSIMDExpandImm(IValueT Value, Type ElmtTy, IValueT &Op, in encodeAdvSIMDExpandImm() argument
226 switch (ElmtTy) { in encodeAdvSIMDExpandImm()
611 IValueT encodeSIMDShiftImm6(SIMDShiftType Shift, Type ElmtTy, in encodeSIMDShiftImm6() argument
614 const SizeT MaxShift = getScalarIntBitWidth(ElmtTy); in encodeSIMDShiftImm6()
616 assert(ElmtTy == IceType_i8 || ElmtTy == IceType_i16 || in encodeSIMDShiftImm6()
617 ElmtTy == IceType_i32); in encodeSIMDShiftImm6()
623 IValueT encodeSIMDShiftImm6(SIMDShiftType Shift, Type ElmtTy, in encodeSIMDShiftImm6() argument
626 return encodeSIMDShiftImm6(Shift, ElmtTy, Imm); in encodeSIMDShiftImm6()
654 IValueT AssemblerARM32::encodeElmtType(Type ElmtTy) { in encodeElmtType() argument
655 switch (ElmtTy) { in encodeElmtType()
667 typeStdString(ElmtTy)); in encodeElmtType()
1211 void AssemblerARM32::emitSIMD(IValueT Opcode, Type ElmtTy, IValueT Dd, in emitSIMD() argument
1214 const IValueT ElmtSize = encodeElmtType(ElmtTy); in emitSIMD()
1217 isFloatingType(ElmtTy)); in emitSIMD()
1231 void AssemblerARM32::emitSIMDqqq(IValueT Opcode, Type ElmtTy, in emitSIMDqqq() argument
1235 const IValueT ElmtSize = encodeElmtType(ElmtTy); in emitSIMDqqq()
1238 isFloatingType(ElmtTy), OpcodeName); in emitSIMDqqq()
2357 const Type ElmtTy = typeElementType(OpQd->getType()); in vabsq() local
2358 assert(ElmtTy != IceType_i64 && "vabsq doesn't allow i64!"); in vabsq()
2364 B24 | B23 | B21 | B20 | B16 | B9 | B8 | (encodeElmtType(ElmtTy) << 18); in vabsq()
2366 emitSIMDBase(VabsqOpcode, Dd, Dn, Dm, UseQRegs, isFloatingType(ElmtTy)); in vabsq()
2381 void AssemblerARM32::vaddqi(Type ElmtTy, const Operand *OpQd, in vaddqi() argument
2388 assert(isScalarIntegerType(ElmtTy) && in vaddqi()
2392 emitSIMDqqq(VaddqiOpcode, ElmtTy, OpQd, OpQm, OpQn, Vaddqi); in vaddqi()
2428 constexpr Type ElmtTy = IceType_i8; in vandq() local
2429 emitSIMDqqq(VandqOpcode, ElmtTy, OpQd, OpQm, OpQn, Vandq); in vandq()
2440 constexpr Type ElmtTy = IceType_i8; // emits sz=0 in vbslq() local
2441 emitSIMDqqq(VbslqOpcode, ElmtTy, OpQd, OpQm, OpQn, Vbslq); in vbslq()
2444 void AssemblerARM32::vceqqi(const Type ElmtTy, const Operand *OpQd, in vceqqi() argument
2453 emitSIMDqqq(VceqOpcode, ElmtTy, OpQd, OpQm, OpQn, Vceq); in vceqqi()
2464 constexpr Type ElmtTy = IceType_i8; // encoded as 0b00 in vceqqs() local
2465 emitSIMDqqq(VceqOpcode, ElmtTy, OpQd, OpQm, OpQn, Vceq); in vceqqs()
2468 void AssemblerARM32::vcgeqi(const Type ElmtTy, const Operand *OpQd, in vcgeqi() argument
2477 emitSIMDqqq(VcgeOpcode, ElmtTy, OpQd, OpQm, OpQn, Vcge); in vcgeqi()
2480 void AssemblerARM32::vcugeqi(const Type ElmtTy, const Operand *OpQd, in vcugeqi() argument
2489 emitSIMDqqq(VcgeOpcode, ElmtTy, OpQd, OpQm, OpQn, Vcge); in vcugeqi()
2500 constexpr Type ElmtTy = IceType_i8; // encoded as 0b00. in vcgeqs() local
2501 emitSIMDqqq(VcgeOpcode, ElmtTy, OpQd, OpQm, OpQn, Vcge); in vcgeqs()
2504 void AssemblerARM32::vcgtqi(const Type ElmtTy, const Operand *OpQd, in vcgtqi() argument
2513 emitSIMDqqq(VcgeOpcode, ElmtTy, OpQd, OpQm, OpQn, Vcge); in vcgtqi()
2516 void AssemblerARM32::vcugtqi(const Type ElmtTy, const Operand *OpQd, in vcugtqi() argument
2525 emitSIMDqqq(VcgeOpcode, ElmtTy, OpQd, OpQm, OpQn, Vcge); in vcugtqi()
2536 constexpr Type ElmtTy = IceType_i8; // encoded as 0b00. in vcgtqs() local
2537 emitSIMDqqq(VcgeOpcode, ElmtTy, OpQd, OpQm, OpQn, Vcge); in vcgtqs()
3320 void AssemblerARM32::vmulqi(Type ElmtTy, const Operand *OpQd, in vmulqi() argument
3327 assert(isScalarIntegerType(ElmtTy) && in vmulqi()
3329 assert(ElmtTy != IceType_i64 && "vmulqi on i64 vector not allowed"); in vmulqi()
3332 emitSIMDqqq(VmulqiOpcode, ElmtTy, OpQd, OpQn, OpQm, Vmulqi); in vmulqi()
3335 void AssemblerARM32::vmulh(Type ElmtTy, const Operand *OpQd, in vmulh() argument
3345 assert(isScalarIntegerType(ElmtTy) && in vmulh()
3347 assert(ElmtTy != IceType_i64 && "vmull on i64 vector not allowed"); in vmulh()
3351 const IValueT ElmtSize = encodeElmtType(ElmtTy); in vmulh()
3379 void AssemblerARM32::vmlap(Type ElmtTy, const Operand *OpQd, in vmlap() argument
3388 assert(isScalarIntegerType(ElmtTy) && in vmlap()
3390 assert(ElmtTy != IceType_i64 && "vmull on i64 vector not allowed"); in vmlap()
3394 const IValueT ElmtSize = encodeElmtType(ElmtTy); in vmlap()
3415 assert(ElmtTy != IceType_i64 && "vpadd doesn't allow i64!"); in vmlap()
3417 B25 | B11 | B9 | B8 | B4 | ((encodeElmtType(ElmtTy) + 1) << 20); in vmlap()
3421 void AssemblerARM32::vdup(Type ElmtTy, const Operand *OpQd, const Operand *OpQn, in vdup() argument
3440 switch (ElmtTy) { in vdup()
3465 void AssemblerARM32::vzip(Type ElmtTy, const Operand *OpQd, const Operand *OpQn, in vzip() argument
3475 assert(ElmtTy != IceType_i64 && "vzip on i64 vector not allowed"); in vzip()
3497 const IValueT ElmtSize = encodeElmtType(ElmtTy); in vzip()
3500 if (ElmtTy != IceType_i32 && ElmtTy != IceType_f32) { in vzip()
3646 void AssemblerARM32::vnegqs(Type ElmtTy, const Operand *OpQd, in vnegqs() argument
3663 const IValueT ElmtSize = encodeElmtType(ElmtTy); in vnegqs()
3667 isFloatingType(ElmtTy)); in vnegqs()
3678 constexpr Type ElmtTy = IceType_i8; in vorrq() local
3679 emitSIMDqqq(VorrqOpcode, ElmtTy, OpQd, OpQm, OpQn, Vorrq); in vorrq()
3827 void AssemblerARM32::vqaddqi(Type ElmtTy, const Operand *OpQd, in vqaddqi() argument
3834 assert(isScalarIntegerType(ElmtTy) && in vqaddqi()
3838 emitSIMDqqq(VqaddqiOpcode, ElmtTy, OpQd, OpQm, OpQn, Vqaddqi); in vqaddqi()
3841 void AssemblerARM32::vqaddqu(Type ElmtTy, const Operand *OpQd, in vqaddqu() argument
3848 assert(isScalarIntegerType(ElmtTy) && in vqaddqu()
3852 emitSIMDqqq(VqaddquOpcode, ElmtTy, OpQd, OpQm, OpQn, Vqaddqu); in vqaddqu()
3855 void AssemblerARM32::vqsubqi(Type ElmtTy, const Operand *OpQd, in vqsubqi() argument
3862 assert(isScalarIntegerType(ElmtTy) && in vqsubqi()
3866 emitSIMDqqq(VqsubqiOpcode, ElmtTy, OpQd, OpQm, OpQn, Vqsubqi); in vqsubqi()
3869 void AssemblerARM32::vqsubqu(Type ElmtTy, const Operand *OpQd, in vqsubqu() argument
3876 assert(isScalarIntegerType(ElmtTy) && in vqsubqu()
3880 emitSIMDqqq(VqsubquOpcode, ElmtTy, OpQd, OpQm, OpQn, Vqsubqu); in vqsubqu()
3883 void AssemblerARM32::vsubqi(Type ElmtTy, const Operand *OpQd, in vsubqi() argument
3890 assert(isScalarIntegerType(ElmtTy) && in vsubqi()
3894 emitSIMDqqq(VsubqiOpcode, ElmtTy, OpQd, OpQm, OpQn, Vsubqi); in vsubqi()
4008 void AssemblerARM32::vshlqi(Type ElmtTy, const Operand *OpQd, in vshlqi() argument
4015 assert(isScalarIntegerType(ElmtTy) && in vshlqi()
4019 emitSIMDqqq(VshlOpcode, ElmtTy, OpQd, OpQn, OpQm, Vshl); in vshlqi()
4022 void AssemblerARM32::vshlqc(Type ElmtTy, const Operand *OpQd, in vshlqc() argument
4030 assert(isScalarIntegerType(ElmtTy) && in vshlqc()
4035 encodeSIMDShiftImm6(ST_Vshl, ElmtTy, Imm6), Vshl); in vshlqc()
4038 void AssemblerARM32::vshrqc(Type ElmtTy, const Operand *OpQd, in vshrqc() argument
4046 assert(isScalarIntegerType(ElmtTy) && in vshrqc()
4052 encodeSIMDShiftImm6(ST_Vshr, ElmtTy, Imm6), Vshr); in vshrqc()
4055 void AssemblerARM32::vshlqu(Type ElmtTy, const Operand *OpQd, in vshlqu() argument
4062 assert(isScalarIntegerType(ElmtTy) && in vshlqu()
4066 emitSIMDqqq(VshlOpcode, ElmtTy, OpQd, OpQn, OpQm, Vshl); in vshlqu()