Lines Matching refs:OpRt
208 const Operand *OpRt, const char *InsnName) { in emitRsRt() argument
210 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRsRt()
218 void AssemblerMIPS32::emitRtRsImm16(IValueT Opcode, const Operand *OpRt, in emitRtRsImm16() argument
221 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRtRsImm16()
231 void AssemblerMIPS32::emitRtRsImm16Rel(IValueT Opcode, const Operand *OpRt, in emitRtRsImm16Rel() argument
236 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRtRsImm16Rel()
269 const Operand *OpRt, const uint32_t Sa, in emitRdRtSa() argument
272 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRdRtSa()
282 const Operand *OpRs, const Operand *OpRt, in emitRdRsRt() argument
286 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRdRsRt()
342 const Operand *OpRt, in emitCOP1FmtRtFsFd() argument
346 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitCOP1FmtRtFsFd()
356 void AssemblerMIPS32::emitCOP1MovRtFs(IValueT Opcode, const Operand *OpRt, in emitCOP1MovRtFs() argument
359 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitCOP1MovRtFs()
377 void AssemblerMIPS32::addi(const Operand *OpRt, const Operand *OpRs, in addi() argument
380 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "addi"); in addi()
395 void AssemblerMIPS32::addiu(const Operand *OpRt, const Operand *OpRs, in addiu() argument
398 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "addiu"); in addiu()
401 void AssemblerMIPS32::addiu(const Operand *OpRt, const Operand *OpRs, in addiu() argument
404 emitRtRsImm16Rel(Opcode, OpRt, OpRs, OpImm, Reloc, "addiu"); in addiu()
408 const Operand *OpRt) { in addu() argument
410 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "addu"); in addu()
414 const Operand *OpRt) { in and_() argument
416 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "and"); in and_()
419 void AssemblerMIPS32::andi(const Operand *OpRt, const Operand *OpRs, in andi() argument
422 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "andi"); in andi()
565 void AssemblerMIPS32::div(const Operand *OpRs, const Operand *OpRt) { in div() argument
567 emitRsRt(Opcode, OpRs, OpRt, "div"); in div()
582 void AssemblerMIPS32::divu(const Operand *OpRs, const Operand *OpRt) { in divu() argument
584 emitRsRt(Opcode, OpRs, OpRt, "divu"); in divu()
665 void AssemblerMIPS32::lui(const Operand *OpRt, const Operand *OpImm, in lui() argument
668 const IValueT Rt = encodeGPRegister(OpRt, "Rt", "lui"); in lui()
684 void AssemblerMIPS32::ldc1(const Operand *OpRt, const Operand *OpBase, in ldc1() argument
687 const IValueT Rt = encodeFPRegister(OpRt, "Ft", "ldc1"); in ldc1()
705 void AssemblerMIPS32::ll(const Operand *OpRt, const Operand *OpBase, in ll() argument
708 emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "ll"); in ll()
711 void AssemblerMIPS32::lw(const Operand *OpRt, const Operand *OpBase, in lw() argument
713 switch (OpRt->getType()) { in lw()
717 emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "lb"); in lw()
722 emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "lh"); in lw()
727 emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "lw"); in lw()
732 emitFtRsImm16(Opcode, OpRt, OpBase, Offset, "lwc1"); in lw()
737 emitFtRsImm16(Opcode, OpRt, OpBase, Offset, "ldc1"); in lw()
744 void AssemblerMIPS32::lwc1(const Operand *OpRt, const Operand *OpBase, in lwc1() argument
747 const IValueT Rt = encodeFPRegister(OpRt, "Ft", "lwc1"); in lwc1()
765 void AssemblerMIPS32::mfc1(const Operand *OpRt, const Operand *OpFs) { in mfc1() argument
767 emitCOP1MovRtFs(Opcode, OpRt, OpFs, "mfc1"); in mfc1()
851 const Operand *OpRt) { in movn() argument
853 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "movn"); in movn()
892 const Operand *OpRt) { in movz() argument
894 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "movz"); in movz()
903 void AssemblerMIPS32::mtc1(const Operand *OpRt, const Operand *OpFs) { in mtc1() argument
905 emitCOP1MovRtFs(Opcode, OpRt, OpFs, "mtc1"); in mtc1()
923 const Operand *OpRt) { in mul() argument
925 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "mul"); in mul()
940 void AssemblerMIPS32::mult(const Operand *OpRs, const Operand *OpRt) { in mult() argument
942 emitRsRt(Opcode, OpRs, OpRt, "mult"); in mult()
945 void AssemblerMIPS32::multu(const Operand *OpRs, const Operand *OpRt) { in multu() argument
947 emitRsRt(Opcode, OpRs, OpRt, "multu"); in multu()
951 const Operand *OpRt) { in nor() argument
953 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "nor"); in nor()
957 const Operand *OpRt) { in or_() argument
959 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "or"); in or_()
962 void AssemblerMIPS32::ori(const Operand *OpRt, const Operand *OpRs, in ori() argument
965 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "ori"); in ori()
974 void AssemblerMIPS32::sc(const Operand *OpRt, const Operand *OpBase, in sc() argument
977 emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "sc"); in sc()
980 void AssemblerMIPS32::sll(const Operand *OpRd, const Operand *OpRt, in sll() argument
983 emitRdRtSa(Opcode, OpRd, OpRt, Sa, "sll"); in sll()
986 void AssemblerMIPS32::sllv(const Operand *OpRd, const Operand *OpRt, in sllv() argument
989 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "sllv"); in sllv()
993 const Operand *OpRt) { in slt() argument
995 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "slt"); in slt()
998 void AssemblerMIPS32::slti(const Operand *OpRt, const Operand *OpRs, in slti() argument
1001 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "slti"); in slti()
1005 const Operand *OpRt) { in sltu() argument
1007 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "sltu"); in sltu()
1010 void AssemblerMIPS32::sltiu(const Operand *OpRt, const Operand *OpRs, in sltiu() argument
1013 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "sltiu"); in sltiu()
1026 void AssemblerMIPS32::sra(const Operand *OpRd, const Operand *OpRt, in sra() argument
1029 emitRdRtSa(Opcode, OpRd, OpRt, Sa, "sra"); in sra()
1032 void AssemblerMIPS32::srl(const Operand *OpRd, const Operand *OpRt, in srl() argument
1035 emitRdRtSa(Opcode, OpRd, OpRt, Sa, "srl"); in srl()
1038 void AssemblerMIPS32::srav(const Operand *OpRd, const Operand *OpRt, in srav() argument
1041 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "srav"); in srav()
1044 void AssemblerMIPS32::srlv(const Operand *OpRd, const Operand *OpRt, in srlv() argument
1047 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "srlv"); in srlv()
1063 const Operand *OpRt) { in subu() argument
1065 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "subu"); in subu()
1068 void AssemblerMIPS32::sdc1(const Operand *OpRt, const Operand *OpBase, in sdc1() argument
1071 const IValueT Rt = encodeFPRegister(OpRt, "Ft", "sdc1"); in sdc1()
1089 void AssemblerMIPS32::sw(const Operand *OpRt, const Operand *OpBase, in sw() argument
1091 switch (OpRt->getType()) { in sw()
1095 emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "sb"); in sw()
1100 emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "sh"); in sw()
1105 emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "sw"); in sw()
1110 emitFtRsImm16(Opcode, OpRt, OpBase, Offset, "swc1"); in sw()
1115 emitFtRsImm16(Opcode, OpRt, OpBase, Offset, "sdc1"); in sw()
1122 void AssemblerMIPS32::swc1(const Operand *OpRt, const Operand *OpBase, in swc1() argument
1125 const IValueT Rt = encodeFPRegister(OpRt, "Ft", "swc1"); in swc1()
1148 void AssemblerMIPS32::teq(const Operand *OpRs, const Operand *OpRt, in teq() argument
1152 const IValueT Rt = encodeGPRegister(OpRt, "Rt", "teq"); in teq()
1180 const Operand *OpRt) { in xor_() argument
1182 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "xor"); in xor_()
1185 void AssemblerMIPS32::xori(const Operand *OpRt, const Operand *OpRs, in xori() argument
1188 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "xori"); in xori()
1192 const Operand *OpRt, IOffsetT Offset) { in emitBr() argument
1230 if (OpRt != nullptr) { in emitBr()
1231 IValueT Rt = encodeGPRegister(OpRt, "Rt", "branch"); in emitBr()
1241 const Operand *OpRt, Label *TargetLabel) { in bcc() argument
1244 emitBr(Cond, OpRs, OpRt, Dest); in bcc()
1251 emitBr(Cond, OpRs, OpRt, PrevPosition); in bcc()