Lines Matching refs:Src0
804 Operand *&Src0, Operand *&Src1) {
805 if (Src0 == LoadDest && Src1 != LoadDest) {
806 Src0 = LoadSrc;
809 if (Src0 != LoadDest && Src1 == LoadDest) {
855 Operand *Src0 = Arith->getSrc(0);
857 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) {
859 Arith->getDest(), Src0, Src1);
862 Operand *Src0 = Icmp->getSrc(0);
864 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) {
866 Icmp->getDest(), Src0, Src1);
869 Operand *Src0 = Fcmp->getSrc(0);
871 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) {
873 Fcmp->getDest(), Src0, Src1);
876 Operand *Src0 = Select->getTrueOperand();
878 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) {
880 Select->getCondition(), Src0, Src1);
884 auto *Src0 = llvm::dyn_cast<Variable>(Cast->getSrc(0));
885 if (Src0 == LoadDest) {
1615 bool TargetX86Base<TraitsType>::optimizeScalarMul(Variable *Dest, Operand *Src0,
1624 _mov(T, Src0);
1635 _mov(T, Src0);
1682 if (typeWidthInBytes(Src0->getType()) < typeWidthInBytes(T->getType())) {
1683 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
1686 _mov(T, Src0);
1931 Operand *Src0 = legalize(Instr->getSrc(0));
1935 if (!llvm::isa<Variable>(Src0) && llvm::isa<Variable>(Src1)) {
1936 std::swap(Src0, Src1);
1939 if (llvm::isa<Constant>(Src0) && !llvm::isa<Constant>(Src1)) {
1940 std::swap(Src0, Src1);
1945 if (!Instr->isLastUse(Src0) && Instr->isLastUse(Src1)) {
1946 std::swap(Src0, Src1);
1972 Operand *Src0Lo = loOperand(Src0);
1973 Operand *Src0Hi = hiOperand(Src0);
2085 _movp(T, Src0);
2091 _movp(T, Src0);
2097 _movp(T, Src0);
2103 _movp(T, Src0);
2109 _movp(T, Src0);
2119 _movp(T, Src0);
2120 _pmull(T, Src0 == Src1 ? T : Src1);
2152 _movp(T1, Src0);
2153 _pshufd(T2, Src0, Mask1030);
2169 _movp(T, Src0);
2176 _movp(T, Src0);
2183 _movp(T, Src0);
2195 _movp(T, Src0);
2201 _movp(T, Src0);
2207 _movp(T, Src0);
2208 _mulps(T, Src0 == Src1 ? T : Src1);
2213 _movp(T, Src0);
2237 auto *Var = legalizeToReg(Src0);
2244 _mov(T, Src0);
2249 _mov(T, Src0);
2254 _mov(T, Src0);
2259 _mov(T, Src0);
2264 _mov(T, Src0);
2270 if (optimizeScalarMul(Dest, Src0, C->getValue()))
2276 _mov(T, Src0, Traits::RegisterSet::Reg_al);
2278 _imul(T, Src0 == Src1 ? T : Src1);
2282 _imul_imm(T, Src0, ImmConst);
2285 _mov(T, Src0);
2286 _imul(T, Src0 == Src1 ? T : Src1);
2291 _mov(T, Src0);
2299 _mov(T, Src0);
2307 _mov(T, Src0);
2341 _mov(T, Src0, Eax);
2366 _mov(T, Src0);
2374 _add(T, Src0);
2388 _mov(T, Src0, Traits::getRaxOrDie());
2392 _mov(T, Src0, Traits::RegisterSet::Reg_eax);
2396 _mov(T, Src0, Traits::RegisterSet::Reg_ax);
2400 _mov(T, Src0, Traits::RegisterSet::Reg_al);
2434 _mov(T, Src0, Eax);
2473 _mov(T, Src0);
2478 _add(T, Src0);
2480 _sub(T, Src0);
2511 _mov(T, Src0, Eax);
2526 _mov(T, Src0);
2531 _mov(T, Src0);
2536 _mov(T, Src0);
2537 _mulss(T, Src0 == Src1 ? T : Src1);
2541 _mov(T, Src0);
2592 Operand *Src0 = legalize(Cond, Legal_Reg | Legal_Mem);
2594 _cmp(Src0, Zero);
2955 Operand *Src0 = legalizeUndef(Instr->getSrc(0));
2956 if (!Traits::Is64Bit && Src0->getType() == IceType_i64)
2957 Src0 = loOperand(Src0);
2958 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
2964 Operand *Src0 = legalizeUndef(Instr->getSrc(0));
2965 if (!Traits::Is64Bit && Src0->getType() == IceType_i64)
2966 Src0 = loOperand(Src0);
2967 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
3079 Operand *Src0 = Instr->getSrc(0);
3080 if (isVectorType(Src0->getType())) {
3082 } else if (Src0->getType() == IceType_i64 ||
3083 (!Traits::Is64Bit && Src0->getType() == IceType_i32)) {
3086 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
3108 Operand *Src0 = Instr->getSrc(0);
3109 if (DestTy == Src0->getType()) {
3110 auto *Assign = InstAssign::create(Func, Dest, Src0);
3125 Variable *Src0R = legalizeToReg(Src0);
3131 assert(Src0->getType() == IceType_f64);
3133 Variable *Src0R = legalizeToReg(Src0);
3138 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
3172 assert(Src0->getType() == IceType_i64);
3174 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
3179 Src0 = legalize(Src0);
3180 if (llvm::isa<X86OperandMem>(Src0)) {
3182 _movq(T, Src0);
3202 _mov(T_Lo, loOperand(Src0));
3208 _mov(T_Hi, hiOperand(Src0));
3223 if (Src0->getType() == IceType_i32) {
3229 _movd(Dest, legalize(Src0, Legal_Reg | Legal_Mem));
3231 _movp(Dest, legalizeToReg(Src0));
3336 Operand *Src0 = Fcmp->getSrc(0);
3370 std::swap(Src0, Src1);
3374 Src0 = legalize(Src0);
3377 _mov(T, Src0);
3441 Operand *Src0 = Fcmp->getSrc(0);
3452 std::swap(Src0, Src1);
3462 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
3514 Operand *Src0 = legalize(Icmp->getSrc(0));
3525 if (!Traits::Is64Bit && Src0->getType() == IceType_i64) {
3543 Operand *Src0RM = legalizeSrc0ForCmp(Src0, Src1);
3551 Operand *Src0 = legalize(Icmp->getSrc(0));
3558 Type Ty = Src0->getType();
3578 lowerCast(InstCast::create(Func, InstCast::Sext, NewSrc0, Src0));
3580 Src0 = NewSrc0;
3587 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
3671 Operand *Src0 = legalize(Icmp->getSrc(0));
3694 Src0LoRM = legalize(loOperand(Src0), Legal_Reg | Legal_Mem);
3699 Src0HiRM = legalize(hiOperand(Src0), Legal_Reg | Legal_Mem);
3708 Src0LoRM = legalize(loOperand(Src0), Legal_Reg | Legal_Mem);
3709 Src0HiRM = legalize(hiOperand(Src0), Legal_Reg | Legal_Mem);
3868 Operand *Src0 = legalize(Arith->getSrc(0));
3876 _mov(T, Src0);
3886 _mov(T, Src0);
4458 Operand *Src0 = Instr->getArg(0);
4461 auto *T = makeReg(Src0->getType());
4462 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
4470 Operand *Src0 = Instr->getArg(0);
4473 auto *T = makeReg(Src0->getType());
4474 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
4497 Operand *Src0 = Instr->getArg(0);
4501 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
4509 Operand *Src0 = Instr->getArg(0);
4513 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
4521 Operand *Src0 = Instr->getArg(0);
4525 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
4533 Operand *Src0 = Instr->getArg(0);
4537 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
4545 Operand *Src0 = Instr->getArg(0);
4549 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
4557 Operand *Src0 = Instr->getArg(0);
4561 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
4569 Operand *Src0 = Instr->getArg(0);
4573 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
5621 Operand *Src0 = ArithInst->getSrc(0);
5623 auto *Var0 = llvm::dyn_cast<Variable>(Src0);
5625 auto *Const0 = llvm::dyn_cast<ConstantInteger32>(Src0);
5627 auto *Reloc0 = llvm::dyn_cast<ConstantRelocatable>(Src0);
5976 Operand *Src0 = formMemoryOperand(Load->getSourceAddress(), Ty);
5977 doMockBoundsCheck(Src0);
5978 auto *Assign = InstAssign::create(Func, DestLoad, Src0);
6104 Operand *Src0, SizeT Index0, SizeT Index1, Operand *Src1, SizeT Index2,
6111 const Type SrcTy = Src0->getType();
6114 auto *Src0R = legalizeToReg(Src0);
6125 Operand *Src0, SizeT Index0, Operand *Src1, SizeT Index1) {
6126 return lowerShuffleVector_TwoFromSameSrc(Src0, Index0, IGNORE_INDEX, Src1,
6184 Variable *Dest, Operand *Src0, Operand *Src1, int8_t Idx0, int8_t Idx1,
6211 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
6246 auto *Src0 = Instr->getSrc(0);
6263 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
6273 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
6284 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
6294 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
6324 lowerShuffleVector_UsingPshufb(Dest, Src0, Src1, Index0, Index1, Index2,
6338 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
6347 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
6357 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
6366 auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
6390 Dest, Src0, Src1, TO_BYTE_INDEX(Index0), TO_BYTE_INDEX(Index0) + 1,
6415 T = lowerShuffleVector_AllFromSameSrc(Src0, Index0, Index1, Index2,
6422 auto *Unified = lowerShuffleVector_UnifyFromDifferentSrcs(Src0, Index2,
6424 T = lowerShuffleVector_TwoFromSameSrc(Src0, Index0, Index1, Unified,
6430 Src0, Index3);
6431 T = lowerShuffleVector_TwoFromSameSrc(Src0, Index0, Index1, Unified,
6436 T = lowerShuffleVector_TwoFromSameSrc(Src0, Index0, Index1, Src1,
6441 auto *Unified = lowerShuffleVector_UnifyFromDifferentSrcs(Src0, Index0,
6444 Unified, UNIFIED_INDEX_0, UNIFIED_INDEX_1, Src0, Index2, Index3);
6451 auto *Src0R = legalizeToReg(Src0);
6459 Src0, Index0, Src1, Index1);
6465 Src0, Index0, Src1, Index1);
6467 Src0, Index2, Src1, Index3);
6477 Src0, Index0, Src1, Index1);
6483 Src0, Index0, Src1, Index1);
6485 Src1, Index2, Src0, Index3);
6495 auto *Unified = lowerShuffleVector_UnifyFromDifferentSrcs(Src0, Index0,
6503 Src0, Index1);
6505 Unified, UNIFIED_INDEX_0, UNIFIED_INDEX_1, Src0, Index2, Index3);
6513 Src1, Index0, Src0, Index1);
6521 Src1, Index0, Src0, Index1);
6523 Src0, Index2, Src1, Index3);
6533 auto *Src1RM = legalize(Src0, Legal_Reg | Legal_Mem);
6540 Src1, Index0, Src0, Index1);
6546 Src1, Index0, Src0, Index1);
6548 Src1, Index2, Src0, Index3);
6559 Src0, Index1);
6565 T = lowerShuffleVector_TwoFromSameSrc(Src1, Index0, Index1, Src0,
6572 auto *Unified = lowerShuffleVector_UnifyFromDifferentSrcs(Src0, Index2,
6580 Src0, Index3);
6611 InstExtractElement::create(Func, ExtElmt, Src0, Index));
7054 Operand *Src0 = Instr->getComparison();
7059 if (!Traits::Is64Bit && Src0->getType() == IceType_i64) {
7060 Src0 = legalize(Src0); // get Base/Index into physical registers
7061 Operand *Src0Lo = loOperand(Src0);
7062 Operand *Src0Hi = hiOperand(Src0);
7093 Src0 = Src0Lo;
7103 lowerCaseCluster(CaseClusters.front(), Src0, DoneCmp, DefaultTarget);
7108 Variable *Comparison = legalizeToReg(Src0);
7376 Operand *Src0 = Arith->getSrc(0);
7383 scalarizeArithmetic(Arith->getOp(), Dest, Src0, Src1);
7398 scalarizeArithmetic(Arith->getOp(), Dest, Src0, Src1);
7422 Operand *Src0 = Cast->getSrc(0);
7423 const Type SrcType = Src0->getType();
7494 if (DestTy == Src0->getType())
7500 assert(Src0->getType() == IceType_v8i1);
7505 assert(Src0->getType() == IceType_v16i1);
7510 assert(Src0->getType() == IceType_i8);
7514 Context.insert<InstCast>(InstCast::Zext, Src0AsI32, Src0);
7515 Src0 = Src0AsI32;
7518 assert(Src0->getType() == IceType_i16);
7522 Context.insert<InstCast>(InstCast::Zext, Src0AsI32, Src0);
7523 Src0 = Src0AsI32;
7530 Call->addArg(Src0);
8057 Operand *TargetX86Base<TraitsType>::legalizeSrc0ForCmp(Operand *Src0,
8066 return legalize(Src0, IsSrc1ImmOrReg ? (Legal_Reg | Legal_Mem) : Legal_Reg);