Lines Matching refs:Inst0
709 #define TestImplRegReg(Inst0, Inst1, Dst0, Dst1, Value0, Src0, Src1, Value1, \ in TEST_F() argument
715 "(" #Inst0 ", " #Inst1 ", " #Dst0 ", " #Dst1 ", " #Value0 ", " #Src0 \ in TEST_F()
725 __ Inst0(IceType_i##Size, Encoded_GPR_##Dst0(), Encoded_GPR_##Src0()); \ in TEST_F()
741 #define TestImplRegAddr(Inst0, Inst1, Dst0, Dst1, Value0, Value1, Op, Size) \ in TEST_F() argument
746 "(" #Inst0 ", " #Inst1 ", " #Dst0 ", " #Dst1 ", " #Value0 \ in TEST_F()
756 __ Inst0(IceType_i##Size, Encoded_GPR_##Dst0(), dwordAddress(T0)); \ in TEST_F()
774 #define TestImplRegImm(Inst0, Inst1, Dst0, Dst1, Value0, Imm, Op, Size) \ in TEST_F() argument
779 "(" #Inst0 ", " #Inst1 ", " #Dst0 ", " #Dst1 ", " #Value0 \ in TEST_F()
785 __ Inst0(IceType_i##Size, Encoded_GPR_##Dst0(), \ in TEST_F()
803 #define TestImplAddrReg(Inst0, Inst1, Value0, Src0, Src1, Value1, Op, Size) \ in TEST_F() argument
808 "(" #Inst0 ", " #Inst1 ", Addr, " #Value0 ", " #Src0 ", " #Src1 \ in TEST_F()
818 __ Inst0(IceType_i##Size, dwordAddress(T0), Encoded_GPR_##Src0()); \ in TEST_F()
836 #define TestImplAddrImm(Inst0, Inst1, Value0, Imm, Op, Size) \ in TEST_F() argument
841 "(" #Inst0 ", " #Inst1 ", Addr, " #Value0 ", Imm(" #Imm "), " #Op \ in TEST_F()
847 __ Inst0(IceType_i##Size, dwordAddress(T0), \ in TEST_F()
867 #define TestImplOp(Inst0, Inst1, Dst0, Dst1, Value0, Src0, Src1, Value1, Op, \ in TEST_F() argument
870 TestImplRegReg(Inst0, Inst1, Dst0, Dst1, Value0, Src0, Src1, Value1, Op, \ in TEST_F()
872 TestImplRegAddr(Inst0, Inst1, Dst0, Dst1, Value0, Value1, Op, Size); \ in TEST_F()
873 TestImplRegImm(Inst0, Inst1, Dst0, Dst1, Value0, Value1, Op, Size); \ in TEST_F()
874 TestImplAddrReg(Inst0, Inst1, Value0, Src0, Src1, Value1, Op, Size); \ in TEST_F()
875 TestImplAddrImm(Inst0, Inst1, Value0, Value1, Op, Size); \ in TEST_F()