Lines Matching refs:write_aux_reg
287 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); in __slc_entire_op()
290 write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1); in __slc_entire_op()
292 write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1); in __slc_entire_op()
315 write_aux_reg(ARC_AUX_SLC_RGN_END1, 0); in slc_upper_region_init()
316 write_aux_reg(ARC_AUX_SLC_RGN_START1, 0); in slc_upper_region_init()
348 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); in __slc_rgn_op()
362 write_aux_reg(ARC_AUX_SLC_RGN_END, end); in __slc_rgn_op()
363 write_aux_reg(ARC_AUX_SLC_RGN_START, paddr); in __slc_rgn_op()
401 write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, in arc_ioc_setup()
404 write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); in arc_ioc_setup()
405 write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); in arc_ioc_setup()
406 write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); in arc_ioc_setup()
479 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & in icache_enable()
490 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | in icache_disable()
501 write_aux_reg(ARC_AUX_IC_IVIC, 1); in __ic_entire_invalidate()
536 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & in dcache_enable()
556 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | in dcache_disable()
577 write_aux_reg(ARC_AUX_DC_PTAG, paddr); in __dcache_line_loop()
579 write_aux_reg(aux_cmd, paddr); in __dcache_line_loop()
596 write_aux_reg(ARC_AUX_DC_CTRL, ctrl); in __before_dc_op()
619 write_aux_reg(aux, 0x1); in __dc_entire_op()