Lines Matching refs:clks
101 clocks = <&clks IMX7D_CLK_ARM>;
121 clocks = <&clks IMX7D_USB_PHY1_CLK>;
128 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
195 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
227 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
240 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
277 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
304 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
318 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
436 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
443 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
451 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
459 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
473 clocks = <&clks IMX7D_CLK_DUMMY>,
474 <&clks IMX7D_GPT1_ROOT_CLK>;
482 clocks = <&clks IMX7D_CLK_DUMMY>,
483 <&clks IMX7D_GPT2_ROOT_CLK>;
492 clocks = <&clks IMX7D_CLK_DUMMY>,
493 <&clks IMX7D_GPT3_ROOT_CLK>;
502 clocks = <&clks IMX7D_CLK_DUMMY>,
503 <&clks IMX7D_GPT4_ROOT_CLK>;
512 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
532 clocks = <&clks IMX7D_OCOTP_CLK>;
550 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
588 clocks = <&clks IMX7D_SNVS_CLK>;
609 clks: ccm@30380000 { label
659 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
668 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
679 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
680 <&clks IMX7D_ECSPI4_ROOT_CLK>;
689 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
690 <&clks IMX7D_PWM1_ROOT_CLK>;
700 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
701 <&clks IMX7D_PWM2_ROOT_CLK>;
711 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
712 <&clks IMX7D_PWM3_ROOT_CLK>;
722 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
723 <&clks IMX7D_PWM4_ROOT_CLK>;
733 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
734 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
760 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
761 <&clks IMX7D_ECSPI1_ROOT_CLK>;
772 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
773 <&clks IMX7D_ECSPI2_ROOT_CLK>;
784 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
785 <&clks IMX7D_ECSPI3_ROOT_CLK>;
795 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
796 <&clks IMX7D_UART1_ROOT_CLK>;
806 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
807 <&clks IMX7D_UART2_ROOT_CLK>;
817 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
818 <&clks IMX7D_UART3_ROOT_CLK>;
828 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
829 <&clks IMX7D_SAI1_ROOT_CLK>,
830 <&clks IMX7D_CLK_DUMMY>,
831 <&clks IMX7D_CLK_DUMMY>;
843 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
844 <&clks IMX7D_SAI2_ROOT_CLK>,
845 <&clks IMX7D_CLK_DUMMY>,
846 <&clks IMX7D_CLK_DUMMY>;
858 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
859 <&clks IMX7D_SAI3_ROOT_CLK>,
860 <&clks IMX7D_CLK_DUMMY>,
861 <&clks IMX7D_CLK_DUMMY>;
876 clocks = <&clks IMX7D_CAAM_CLK>,
877 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
903 clocks = <&clks IMX7D_CLK_DUMMY>,
904 <&clks IMX7D_CAN1_ROOT_CLK>;
913 clocks = <&clks IMX7D_CLK_DUMMY>,
914 <&clks IMX7D_CAN2_ROOT_CLK>;
925 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
935 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
945 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
955 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
964 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
965 <&clks IMX7D_UART4_ROOT_CLK>;
975 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
976 <&clks IMX7D_UART5_ROOT_CLK>;
986 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
987 <&clks IMX7D_UART6_ROOT_CLK>;
997 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
998 <&clks IMX7D_UART7_ROOT_CLK>;
1007 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1018 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1043 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1044 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1045 <&clks IMX7D_USDHC1_ROOT_CLK>;
1055 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1056 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1057 <&clks IMX7D_USDHC2_ROOT_CLK>;
1067 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1068 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1069 <&clks IMX7D_USDHC3_ROOT_CLK>;
1079 clocks = <&clks IMX7D_SDMA_CORE_CLK>,
1080 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
1094 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1095 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1096 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1097 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1098 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1117 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1128 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1129 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1134 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1135 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;