Lines Matching refs:clks
159 clocks = <&clks IMX7ULP_CLK_DMA1>, <&clks IMX7ULP_CLK_DMA_MUX1>;
193 clocks = <&clks IMX7ULP_CLK_SNVS>;
201 clocks = <&clks IMX7ULP_CLK_LPTPM5>;
209 clocks = <&clks IMX7ULP_CLK_LPIT1>;
211 assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>;
212 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
219 clocks = <&clks IMX7ULP_CLK_LPI2C4>;
221 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>;
222 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
231 clocks = <&clks IMX7ULP_CLK_LPI2C5>;
233 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>;
234 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
243 clocks = <&clks IMX7ULP_CLK_LPSPI2>;
245 assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>;
246 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
255 clocks = <&clks IMX7ULP_CLK_LPSPI3>;
257 assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>;
258 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
267 clocks = <&clks IMX7ULP_CLK_LPUART4>;
269 assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>;
270 assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>;
279 clocks = <&clks IMX7ULP_CLK_LPUART5>;
281 assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>;
282 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
294 clocks = <&clks IMX7ULP_CLK_USB0>;
315 clocks = <&clks IMX7ULP_CLK_USB_PHY>;
323 clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
324 <&clks IMX7ULP_CLK_NIC1_DIV>,
325 <&clks IMX7ULP_CLK_USDHC0>;
337 clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
338 <&clks IMX7ULP_CLK_NIC1_DIV>,
339 <&clks IMX7ULP_CLK_USDHC1>;
351 clocks = <&clks IMX7ULP_CLK_WDG1>;
352 assigned-clocks = <&clks IMX7ULP_CLK_WDG1>;
353 assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
366 clocks = <&clks IMX7ULP_CLK_WDG2>;
367 assigned-clocks = <&clks IMX7ULP_CLK_WDG2>;
368 assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
372 clks: scg1@403E0000 { label
380 assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>,
381 <&clks IMX7ULP_CLK_USDHC1>;
382 assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>,
383 <&clks IMX7ULP_CLK_NIC1_DIV>;
414 clocks = <&clks IMX7ULP_CLK_LPI2C6>;
416 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C6>;
417 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
426 clocks = <&clks IMX7ULP_CLK_LPI2C7>;
428 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C7>;
429 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
438 clocks = <&clks IMX7ULP_CLK_LPUART6>;
440 assigned-clocks = <&clks IMX7ULP_CLK_LPUART6>;
441 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
452 clocks = <&clks IMX7ULP_CLK_LPUART7>;
454 assigned-clocks = <&clks IMX7ULP_CLK_LPUART7>;
455 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
466 clocks = <&clks IMX7ULP_CLK_DUMMY>,
467 <&clks IMX7ULP_CLK_LCDIF>,
468 <&clks IMX7ULP_CLK_DUMMY>;
477 clocks = <&clks IMX7ULP_CLK_DSI>;
567 clocks = <&clks IMX7ULP_CLK_DUMMY>,
568 <&clks IMX7ULP_CLK_DUMMY>;
582 clocks = <&clks IMX7ULP_CLK_GPU3D>,
583 <&clks IMX7ULP_CLK_NIC1_DIV>,
584 <&clks IMX7ULP_CLK_GPU_DIV>,
585 <&clks IMX7ULP_CLK_GPU2D>,
586 <&clks IMX7ULP_CLK_NIC1_DIV>,
587 <&clks IMX7ULP_CLK_NIC1_DIV>;