Lines Matching full:offset
80 unsigned int wkclkstctrl; /* offset 0x00 */
81 unsigned int wkctrlclkctrl; /* offset 0x04 */
82 unsigned int wkgpio0clkctrl; /* offset 0x08 */
83 unsigned int wkl4wkclkctrl; /* offset 0x0c */
84 unsigned int timer0clkctrl; /* offset 0x10 */
86 unsigned int idlestdpllmpu; /* offset 0x20 */
89 unsigned int clkseldpllmpu; /* offset 0x2c */
91 unsigned int idlestdpllddr; /* offset 0x34 */
93 unsigned int clkseldpllddr; /* offset 0x40 */
95 unsigned int clkseldplldisp; /* offset 0x54 */
97 unsigned int idlestdpllcore; /* offset 0x5c */
99 unsigned int clkseldpllcore; /* offset 0x68 */
101 unsigned int idlestdpllper; /* offset 0x70 */
103 unsigned int clkdcoldodpllper; /* offset 0x7c */
104 unsigned int divm4dpllcore; /* offset 0x80 */
105 unsigned int divm5dpllcore; /* offset 0x84 */
106 unsigned int clkmoddpllmpu; /* offset 0x88 */
107 unsigned int clkmoddpllper; /* offset 0x8c */
108 unsigned int clkmoddpllcore; /* offset 0x90 */
109 unsigned int clkmoddpllddr; /* offset 0x94 */
110 unsigned int clkmoddplldisp; /* offset 0x98 */
111 unsigned int clkseldpllper; /* offset 0x9c */
112 unsigned int divm2dpllddr; /* offset 0xA0 */
113 unsigned int divm2dplldisp; /* offset 0xA4 */
114 unsigned int divm2dpllmpu; /* offset 0xA8 */
115 unsigned int divm2dpllper; /* offset 0xAC */
117 unsigned int wkup_uart0ctrl; /* offset 0xB4 */
118 unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
119 unsigned int wkup_adctscctrl; /* offset 0xBC */
121 unsigned int timer1clkctrl; /* offset 0xC4 */
123 unsigned int divm6dpllcore; /* offset 0xD8 */
131 unsigned int l4lsclkstctrl; /* offset 0x00 */
132 unsigned int l3sclkstctrl; /* offset 0x04 */
133 unsigned int l4fwclkstctrl; /* offset 0x08 */
134 unsigned int l3clkstctrl; /* offset 0x0c */
136 unsigned int cpgmac0clkctrl; /* offset 0x14 */
137 unsigned int lcdclkctrl; /* offset 0x18 */
138 unsigned int usb0clkctrl; /* offset 0x1C */
140 unsigned int tptc0clkctrl; /* offset 0x24 */
141 unsigned int emifclkctrl; /* offset 0x28 */
142 unsigned int ocmcramclkctrl; /* offset 0x2c */
143 unsigned int gpmcclkctrl; /* offset 0x30 */
144 unsigned int mcasp0clkctrl; /* offset 0x34 */
145 unsigned int uart5clkctrl; /* offset 0x38 */
146 unsigned int mmc0clkctrl; /* offset 0x3C */
147 unsigned int elmclkctrl; /* offset 0x40 */
148 unsigned int i2c2clkctrl; /* offset 0x44 */
149 unsigned int i2c1clkctrl; /* offset 0x48 */
150 unsigned int spi0clkctrl; /* offset 0x4C */
151 unsigned int spi1clkctrl; /* offset 0x50 */
153 unsigned int l4lsclkctrl; /* offset 0x60 */
154 unsigned int l4fwclkctrl; /* offset 0x64 */
155 unsigned int mcasp1clkctrl; /* offset 0x68 */
156 unsigned int uart1clkctrl; /* offset 0x6C */
157 unsigned int uart2clkctrl; /* offset 0x70 */
158 unsigned int uart3clkctrl; /* offset 0x74 */
159 unsigned int uart4clkctrl; /* offset 0x78 */
160 unsigned int timer7clkctrl; /* offset 0x7C */
161 unsigned int timer2clkctrl; /* offset 0x80 */
162 unsigned int timer3clkctrl; /* offset 0x84 */
163 unsigned int timer4clkctrl; /* offset 0x88 */
165 unsigned int gpio1clkctrl; /* offset 0xAC */
166 unsigned int gpio2clkctrl; /* offset 0xB0 */
167 unsigned int gpio3clkctrl; /* offset 0xB4 */
169 unsigned int tpccclkctrl; /* offset 0xBC */
170 unsigned int dcan0clkctrl; /* offset 0xC0 */
171 unsigned int dcan1clkctrl; /* offset 0xC4 */
173 unsigned int epwmss1clkctrl; /* offset 0xCC */
174 unsigned int emiffwclkctrl; /* offset 0xD0 */
175 unsigned int epwmss0clkctrl; /* offset 0xD4 */
176 unsigned int epwmss2clkctrl; /* offset 0xD8 */
177 unsigned int l3instrclkctrl; /* offset 0xDC */
178 unsigned int l3clkctrl; /* Offset 0xE0 */
180 unsigned int timer5clkctrl; /* offset 0xEC */
181 unsigned int timer6clkctrl; /* offset 0xF0 */
182 unsigned int mmc1clkctrl; /* offset 0xF4 */
183 unsigned int mmc2clkctrl; /* offset 0xF8 */
185 unsigned int l4hsclkstctrl; /* offset 0x11C */
186 unsigned int l4hsclkctrl; /* offset 0x120 */
188 unsigned int cpswclkstctrl; /* offset 0x144 */
189 unsigned int lcdcclkstctrl; /* offset 0x148 */
195 unsigned int clktimer7clk; /* offset 0x04 */
196 unsigned int clktimer2clk; /* offset 0x08 */
197 unsigned int clktimer3clk; /* offset 0x0C */
198 unsigned int clktimer4clk; /* offset 0x10 */
200 unsigned int clktimer5clk; /* offset 0x18 */
201 unsigned int clktimer6clk; /* offset 0x1C */
203 unsigned int clktimer1clk; /* offset 0x28 */
205 unsigned int clklcdcpixelclk; /* offset 0x34 */
217 unsigned int wkl4wkclkctrl; /* offset 0x220 */
219 unsigned int usbphy0clkctrl; /* offset 0x240 */
221 unsigned int usbphy1clkctrl; /* offset 0x248 */
223 unsigned int wkclkstctrl; /* offset 0x300 */
225 unsigned int wkup_i2c0ctrl; /* offset 0x340 */
227 unsigned int wkup_uart0ctrl; /* offset 0x348 */
229 unsigned int wkctrlclkctrl; /* offset 0x360 */
231 unsigned int wkgpio0clkctrl; /* offset 0x368 */
234 unsigned int clkmoddpllcore; /* offset 0x520 */
235 unsigned int idlestdpllcore; /* offset 0x524 */
237 unsigned int clkseldpllcore; /* offset 0x52C */
239 unsigned int divm4dpllcore; /* offset 0x538 */
240 unsigned int divm5dpllcore; /* offset 0x53C */
241 unsigned int divm6dpllcore; /* offset 0x540 */
244 unsigned int clkmoddpllmpu; /* offset 0x560 */
245 unsigned int idlestdpllmpu; /* offset 0x564 */
247 unsigned int clkseldpllmpu; /* offset 0x56c */
248 unsigned int divm2dpllmpu; /* offset 0x570 */
251 unsigned int clkmoddpllddr; /* offset 0x5A0 */
252 unsigned int idlestdpllddr; /* offset 0x5A4 */
254 unsigned int clkseldpllddr; /* offset 0x5AC */
255 unsigned int divm2dpllddr; /* offset 0x5B0 */
258 unsigned int clkmoddpllper; /* offset 0x5E0 */
259 unsigned int idlestdpllper; /* offset 0x5E4 */
261 unsigned int clkseldpllper; /* offset 0x5EC */
262 unsigned int divm2dpllper; /* offset 0x5F0 */
264 unsigned int clkdcoldodpllper; /* offset 0x614 */
267 unsigned int clkmoddplldisp; /* offset 0x620 */
269 unsigned int clkseldplldisp; /* offset 0x62C */
270 unsigned int divm2dplldisp; /* offset 0x630 */
278 unsigned int l3clkstctrl; /* offset 0x00 */
280 unsigned int l3clkctrl; /* Offset 0x20 */
282 unsigned int l3instrclkctrl; /* offset 0x40 */
284 unsigned int ocmcramclkctrl; /* offset 0x50 */
286 unsigned int tpccclkctrl; /* offset 0x78 */
288 unsigned int tptc0clkctrl; /* offset 0x80 */
291 unsigned int l4hsclkctrl; /* offset 0x0A0 */
293 unsigned int l4fwclkctrl; /* offset 0x0A8 */
295 unsigned int l3sclkstctrl; /* offset 0x200 */
297 unsigned int gpmcclkctrl; /* offset 0x220 */
299 unsigned int mcasp0clkctrl; /* offset 0x238 */
301 unsigned int mcasp1clkctrl; /* offset 0x240 */
303 unsigned int mmc2clkctrl; /* offset 0x248 */
305 unsigned int qspiclkctrl; /* offset 0x258 */
307 unsigned int usb0clkctrl; /* offset 0x260 */
309 unsigned int usb1clkctrl; /* offset 0x268 */
311 unsigned int l4lsclkstctrl; /* offset 0x400 */
313 unsigned int l4lsclkctrl; /* offset 0x420 */
315 unsigned int dcan0clkctrl; /* offset 0x428 */
317 unsigned int dcan1clkctrl; /* offset 0x430 */
319 unsigned int elmclkctrl; /* offset 0x468 */
322 unsigned int gpio1clkctrl; /* offset 0x478 */
324 unsigned int gpio2clkctrl; /* offset 0x480 */
326 unsigned int gpio3clkctrl; /* offset 0x488 */
328 unsigned int gpio4clkctrl; /* offset 0x490 */
330 unsigned int gpio5clkctrl; /* offset 0x498 */
333 unsigned int i2c1clkctrl; /* offset 0x4A8 */
335 unsigned int i2c2clkctrl; /* offset 0x4B0 */
337 unsigned int mmc0clkctrl; /* offset 0x4C0 */
339 unsigned int mmc1clkctrl; /* offset 0x4C8 */
342 unsigned int spi0clkctrl; /* offset 0x500 */
344 unsigned int spi1clkctrl; /* offset 0x508 */
346 unsigned int timer2clkctrl; /* offset 0x530 */
348 unsigned int timer3clkctrl; /* offset 0x538 */
350 unsigned int timer4clkctrl; /* offset 0x540 */
352 unsigned int timer7clkctrl; /* offset 0x558 */
355 unsigned int uart1clkctrl; /* offset 0x580 */
357 unsigned int uart2clkctrl; /* offset 0x588 */
359 unsigned int uart3clkctrl; /* offset 0x590 */
361 unsigned int uart4clkctrl; /* offset 0x598 */
363 unsigned int uart5clkctrl; /* offset 0x5A0 */
365 unsigned int usbphyocp2scp0clkctrl; /* offset 0x5B8 */
367 unsigned int usbphyocp2scp1clkctrl; /* offset 0x5C0 */
370 unsigned int emifclkstctrl; /* offset 0x700 */
372 unsigned int emifclkctrl; /* offset 0x720 */
374 unsigned int emiffwclkctrl; /* offset 0x730 */
376 unsigned int otfaemifclkctrl; /* offset 0x738 */
378 unsigned int lcdclkctrl; /* offset 0x820 */
380 unsigned int cpswclkstctrl; /* offset 0xB00 */
382 unsigned int cpgmac0clkctrl; /* offset 0xB20 */
395 unsigned int ldo_sram_core_set; /* offset 0x10 */
399 unsigned int io_count; /* offset 0x20 */
403 unsigned int emif_ctrl; /* offset 0x30 */
408 unsigned int clktimer2clk; /* offset 0x04 */
410 unsigned int clkselmacclk; /* offset 0x34 */
416 unsigned int rtcclkctrl; /* offset 0x0 */
417 unsigned int clkstctrl; /* offset 0x4 */
422 unsigned int tidr; /* offset 0x00 */
424 unsigned int tiocp_cfg; /* offset 0x10 */
426 unsigned int tier; /* offset 0x20 */
427 unsigned int tistatr; /* offset 0x24 */
428 unsigned int tistat; /* offset 0x28 */
429 unsigned int tisr; /* offset 0x2c */
430 unsigned int tcicr; /* offset 0x30 */
431 unsigned int twer; /* offset 0x34 */
432 unsigned int tclr; /* offset 0x38 */
433 unsigned int tcrr; /* offset 0x3c */
434 unsigned int tldr; /* offset 0x40 */
435 unsigned int ttgr; /* offset 0x44 */
436 unsigned int twpc; /* offset 0x48 */
437 unsigned int tmar; /* offset 0x4c */
438 unsigned int tcar1; /* offset 0x50 */
439 unsigned int tscir; /* offset 0x54 */
440 unsigned int tcar2; /* offset 0x58 */
446 unsigned int uartsyscfg; /* offset 0x54 */
447 unsigned int uartsyssts; /* offset 0x58 */
460 unsigned int secure_emif_sdram_config; /* offset 0x0110 */
494 unsigned int deviceid; /* offset 0x00 */
496 unsigned int usb_ctrl0; /* offset 0x20 */
498 unsigned int usb_ctrl1; /* offset 0x28 */
500 unsigned int macid0l; /* offset 0x30 */
501 unsigned int macid0h; /* offset 0x34 */
502 unsigned int macid1l; /* offset 0x38 */
503 unsigned int macid1h; /* offset 0x3c */
505 unsigned int miisel; /* offset 0x50 */
507 unsigned int mreqprio_0; /* offset 0x70 */
508 unsigned int mreqprio_1; /* offset 0x74 */
510 unsigned int efuse_sma; /* offset 0x1FC */