Lines Matching full:offset
12 uint pmc_cntrl; /* _CNTRL_0, offset 00 */
13 uint pmc_sec_disable; /* _SEC_DISABLE_0, offset 04 */
14 uint pmc_pmc_swrst; /* _PMC_SWRST_0, offset 08 */
15 uint pmc_wake_mask; /* _WAKE_MASK_0, offset 0C */
16 uint pmc_wake_lvl; /* _WAKE_LVL_0, offset 10 */
17 uint pmc_wake_status; /* _WAKE_STATUS_0, offset 14 */
18 uint pmc_sw_wake_status; /* _SW_WAKE_STATUS_0, offset 18 */
19 uint pmc_dpd_pads_oride; /* _DPD_PADS_ORIDE_0, offset 1C */
20 uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */
21 uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */
22 uint pmc_pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, offset 28 */
24 uint pmc_pwrgate_timer_on; /* _PWRGATE_TIMER_ON_0, offset 2C */
26 uint pmc_clamp_status; /* _CLAMP_STATUS_0, offset 2C */
28 uint pmc_pwrgate_toggle; /* _PWRGATE_TOGGLE_0, offset 30 */
29 uint pmc_remove_clamping; /* _REMOVE_CLAMPING_CMD_0, offset 34 */
30 uint pmc_pwrgate_status; /* _PWRGATE_STATUS_0, offset 38 */
31 uint pmc_pwrgood_timer; /* _PWRGOOD_TIMER_0, offset 3C */
32 uint pmc_blink_timer; /* _BLINK_TIMER_0, offset 40 */
33 uint pmc_no_iopower; /* _NO_IOPOWER_0, offset 44 */
34 uint pmc_pwr_det; /* _PWR_DET_0, offset 48 */
35 uint pmc_pwr_det_latch; /* _PWR_DET_LATCH_0, offset 4C */
37 uint pmc_scratch0; /* _SCRATCH0_0, offset 50 */
38 uint pmc_scratch1; /* _SCRATCH1_0, offset 54 */
39 uint pmc_scratch2; /* _SCRATCH2_0, offset 58 */
40 uint pmc_scratch3; /* _SCRATCH3_0, offset 5C */
41 uint pmc_scratch4; /* _SCRATCH4_0, offset 60 */
42 uint pmc_scratch5; /* _SCRATCH5_0, offset 64 */
43 uint pmc_scratch6; /* _SCRATCH6_0, offset 68 */
44 uint pmc_scratch7; /* _SCRATCH7_0, offset 6C */
45 uint pmc_scratch8; /* _SCRATCH8_0, offset 70 */
46 uint pmc_scratch9; /* _SCRATCH9_0, offset 74 */
47 uint pmc_scratch10; /* _SCRATCH10_0, offset 78 */
48 uint pmc_scratch11; /* _SCRATCH11_0, offset 7C */
49 uint pmc_scratch12; /* _SCRATCH12_0, offset 80 */
50 uint pmc_scratch13; /* _SCRATCH13_0, offset 84 */
51 uint pmc_scratch14; /* _SCRATCH14_0, offset 88 */
52 uint pmc_scratch15; /* _SCRATCH15_0, offset 8C */
53 uint pmc_scratch16; /* _SCRATCH16_0, offset 90 */
54 uint pmc_scratch17; /* _SCRATCH17_0, offset 94 */
55 uint pmc_scratch18; /* _SCRATCH18_0, offset 98 */
56 uint pmc_scratch19; /* _SCRATCH19_0, offset 9C */
57 uint pmc_scratch20; /* _SCRATCH20_0, offset A0 */
58 uint pmc_scratch21; /* _SCRATCH21_0, offset A4 */
59 uint pmc_scratch22; /* _SCRATCH22_0, offset A8 */
60 uint pmc_scratch23; /* _SCRATCH23_0, offset AC */
62 uint pmc_secure_scratch0; /* _SECURE_SCRATCH0_0, offset B0 */
63 uint pmc_secure_scratch1; /* _SECURE_SCRATCH1_0, offset B4 */
64 uint pmc_secure_scratch2; /* _SECURE_SCRATCH2_0, offset B8 */
65 uint pmc_secure_scratch3; /* _SECURE_SCRATCH3_0, offset BC */
66 uint pmc_secure_scratch4; /* _SECURE_SCRATCH4_0, offset C0 */
67 uint pmc_secure_scratch5; /* _SECURE_SCRATCH5_0, offset C4 */
69 uint pmc_cpupwrgood_timer; /* _CPUPWRGOOD_TIMER_0, offset C8 */
70 uint pmc_cpupwroff_timer; /* _CPUPWROFF_TIMER_0, offset CC */
71 uint pmc_pg_mask; /* _PG_MASK_0, offset D0 */
72 uint pmc_pg_mask_1; /* _PG_MASK_1_0, offset D4 */
73 uint pmc_auto_wake_lvl; /* _AUTO_WAKE_LVL_0, offset D8 */
74 uint pmc_auto_wake_lvl_mask; /* _AUTO_WAKE_LVL_MASK_0, offset DC */
75 uint pmc_wake_delay; /* _WAKE_DELAY_0, offset E0 */
76 uint pmc_pwr_det_val; /* _PWR_DET_VAL_0, offset E4 */
77 uint pmc_ddr_pwr; /* _DDR_PWR_0, offset E8 */
78 uint pmc_usb_debounce_del; /* _USB_DEBOUNCE_DEL_0, offset EC */
79 uint pmc_usb_ao; /* _USB_AO_0, offset F0 */
80 uint pmc_crypto_op; /* _CRYPTO_OP__0, offset F4 */
81 uint pmc_pllp_wb0_override; /* _PLLP_WB0_OVERRIDE_0, offset F8 */
83 uint pmc_scratch24; /* _SCRATCH24_0, offset FC */
84 uint pmc_scratch25; /* _SCRATCH24_0, offset 100 */
85 uint pmc_scratch26; /* _SCRATCH24_0, offset 104 */
86 uint pmc_scratch27; /* _SCRATCH24_0, offset 108 */
87 uint pmc_scratch28; /* _SCRATCH24_0, offset 10C */
88 uint pmc_scratch29; /* _SCRATCH24_0, offset 110 */
89 uint pmc_scratch30; /* _SCRATCH24_0, offset 114 */
90 uint pmc_scratch31; /* _SCRATCH24_0, offset 118 */
91 uint pmc_scratch32; /* _SCRATCH24_0, offset 11C */
92 uint pmc_scratch33; /* _SCRATCH24_0, offset 120 */
93 uint pmc_scratch34; /* _SCRATCH24_0, offset 124 */
94 uint pmc_scratch35; /* _SCRATCH24_0, offset 128 */
95 uint pmc_scratch36; /* _SCRATCH24_0, offset 12C */
96 uint pmc_scratch37; /* _SCRATCH24_0, offset 130 */
97 uint pmc_scratch38; /* _SCRATCH24_0, offset 134 */
98 uint pmc_scratch39; /* _SCRATCH24_0, offset 138 */
99 uint pmc_scratch40; /* _SCRATCH24_0, offset 13C */
100 uint pmc_scratch41; /* _SCRATCH24_0, offset 140 */
101 uint pmc_scratch42; /* _SCRATCH24_0, offset 144 */
103 uint pmc_bo_mirror0; /* _BOUNDOUT_MIRROR0_0, offset 148 */
104 uint pmc_bo_mirror1; /* _BOUNDOUT_MIRROR1_0, offset 14C */
105 uint pmc_bo_mirror2; /* _BOUNDOUT_MIRROR2_0, offset 150 */
106 uint pmc_sys_33v_en; /* _SYS_33V_EN_0, offset 154 */
108 uint pmc_gate; /* _GATE_0, offset 15C */
110 uint pmc_wake2_mask; /* _WAKE2_MASK_0, offset 160 */
111 uint pmc_wake2_lvl; /* _WAKE2_LVL_0, offset 164 */
112 uint pmc_wake2_stat; /* _WAKE2_STATUS_0, offset 168 */
113 uint pmc_sw_wake2_stat; /* _SW_WAKE2_STATUS_0, offset 16C */
114 uint pmc_auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, offset 170 */
115 uint pmc_pg_mask2; /* _PG_MASK_2_0, offset 174 */
116 uint pmc_pg_mask_ce1; /* _PG_MASK_CE1_0, offset 178 */
117 uint pmc_pg_mask_ce2; /* _PG_MASK_CE2_0, offset 17C */
118 uint pmc_pg_mask_ce3; /* _PG_MASK_CE3_0, offset 180 */
119 uint pmc_pwrgate_timer_ce0; /* _PWRGATE_TIMER_CE_0_0, offset 184 */
120 uint pmc_pwrgate_timer_ce1; /* _PWRGATE_TIMER_CE_1_0, offset 188 */
121 uint pmc_pwrgate_timer_ce2; /* _PWRGATE_TIMER_CE_2_0, offset 18C */
122 uint pmc_pwrgate_timer_ce3; /* _PWRGATE_TIMER_CE_3_0, offset 190 */
123 uint pmc_pwrgate_timer_ce4; /* _PWRGATE_TIMER_CE_4_0, offset 194 */
124 uint pmc_pwrgate_timer_ce5; /* _PWRGATE_TIMER_CE_5_0, offset 198 */
125 uint pmc_pwrgate_timer_ce6; /* _PWRGATE_TIMER_CE_6_0, offset 19C */
126 uint pmc_pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, offset 1A0 */
127 uint pmc_osc_edpd_over; /* _OSC_EDPD_OVER_0, offset 1A4 */
128 uint pmc_clk_out_cntrl; /* _CLK_OUT_CNTRL_0, offset 1A8 */
129 uint pmc_sata_pwrgate; /* _SATA_PWRGT_0, offset 1AC */
130 uint pmc_sensor_ctrl; /* _SENSOR_CTRL_0, offset 1B0 */
131 uint pmc_reset_status; /* _RTS_STATUS_0, offset 1B4 */
132 uint pmc_io_dpd_req; /* _IO_DPD_REQ_0, offset 1B8 */
133 uint pmc_io_dpd_stat; /* _IO_DPD_STATUS_0, offset 1BC */
134 uint pmc_io_dpd2_req; /* _IO_DPD2_REQ_0, offset 1C0 */
135 uint pmc_io_dpd2_stat; /* _IO_DPD2_STATUS_0, offset 1C4 */
136 uint pmc_sel_dpd_tim; /* _SEL_DPD_TIM_0, offset 1C8 */
137 uint pmc_vddp_sel; /* _VDDP_SEL_0, offset 1CC */
139 uint pmc_ddr_cfg; /* _DDR_CFG_0, offset 1D0 */
140 uint pmc_e_no_vttgen; /* _E_NO_VTTGEN_0, offset 1D4 */
141 uint pmc_reserved0; /* _RESERVED, offset 1D8 */
143 uint pmc_test_pwrgate; /* _TEST_PWRGATE_0, offset 1E0 */
144 uint pmc_pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, offset 1E4 */
145 uint pmc_dsi_sel_dpd; /* _DSI_SEL_DPD_0, offset 1E8 */
148 uint pmc_utmip_pad_cfg; /* _UTMIP_PAD_CFG_0, offset 1F4 */
149 uint pmc_utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */
152 uint pmc_todo_0[9]; /* offset 200-220 */
153 uint pmc_secure_scratch6; /* _SECURE_SCRATCH6_0, offset 224 */
154 uint pmc_secure_scratch7; /* _SECURE_SCRATCH7_0, offset 228 */
155 uint pmc_scratch43; /* _SCRATCH43_0, offset 22C */
156 uint pmc_scratch44; /* _SCRATCH44_0, offset 230 */
167 uint pmc_scratch55; /* _SCRATCH55_0, offset 25C */
168 uint pmc_scratch0_eco; /* _SCRATCH0_ECO_0, offset 260 */
169 uint pmc_por_dpd_ctrl; /* _POR_DPD_CTRL_0, offset 264 */
170 uint pmc_scratch2_eco; /* _SCRATCH2_ECO_0, offset 268 */
172 uint pmc_pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2, offset 2B0 */
173 uint pmc_tsc_mult; /* _TSC_MULT_0, offset 2B4 */
174 uint pmc_cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */
175 uint pmc_glb_amap_cfg; /* _GLB_AMAP_CFG_0, offset 2BC */
176 uint pmc_sticky_bits; /* _STICKY_BITS_0, offset 2C0 */
177 uint pmc_sec_disable2; /* _SEC_DISALBE2, offset 2C4 */
178 uint pmc_weak_bias; /* _WEAK_BIAS_0, offset 2C8 */
180 uint pmc_secure_scratch8; /* _SECURE_SCRATCH8_0, offset 300 */
196 uint pmc_secure_scratch24; /* _SECURE_SCRATCH24_0, offset 340 */
207 uint pmc_secure_scratch35; /* _SECURE_SCRATCH35_0, offset 36C */
210 uint pmc_cntrl2; /* _CNTRL2_0, offset 440 */
212 uint pmc_io_dpd3_req; /* _IO_DPD3_REQ_0, offset 45c */
213 uint pmc_io_dpd3_stat; /* _IO_DPD3_STATUS_0, offset 460 */
214 uint pmc_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 464 */
217 uint pmc_scratch56; /* _SCRATCH56_0, offset 600 */
281 uint pmc_scratch1_eco; /* offset 700 */