33 	setbits_le32(&dv_pll0_regs->pllctl,  in dm365_pll1_init()
48 	setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);  in dm365_pll1_init()
97 	setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);  in dm365_pll1_init()
115 	setbits_le32(&dv_pll1_regs->pllctl,  in dm365_pll2_init()
130 	setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);  in dm365_pll2_init()
174 	setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);  in dm365_pll2_init()
190 	setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);  in dm365_ddr_setup()
197 	setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);  in dm365_ddr_setup()
200 	setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);  in dm365_ddr_setup()
206 	setbits_le32(&dv_sys_module_regs->vtpiocr,  in dm365_ddr_setup()
247 	setbits_le32(&dv_sys_module_regs->vpss_clkctl,  in dm365_vpss_sync_reset()
274 		setbits_le32(TMPSTATUS, FLAG_PORRST);  in dm365_por_reset()
289 		setbits_le32(TMPSTATUS, FLAG_PORRST);  in dm365_wdt_reset()
290 		setbits_le32(TMPSTATUS, FLAG_FLGOFF);  in dm365_wdt_reset()
309 	setbits_le32(TMPSTATUS, FLAG_FLGON);  in dm365_wdt_flag_on()
337 			setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE);  in dm365_psc_init()
366 	setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND);  in dm365_emif_init()
377 	setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value));  in dm365_pinmux_ctl()