Lines Matching refs:r6
49 ldr r6, MDCTL_GEM
50 ldr r7, [r6]
52 str r7, [r6]
55 ldr r6, PTCMD
56 ldr r7, [r6]
58 str r7, [r6]
62 ldr r6, PTSTAT
63 ldr r7, [r6]
69 ldr r6, MDSTAT_GEM
70 ldr r7, [r6]
76 ldr r6, P1394
78 str r10, [r6]
83 ldr r6, DFT_ENABLE
85 str r10, [r6]
87 ldr r6, MMARG_BRF0
89 str r10, [r6]
91 ldr r6, DFT_ENABLE
93 str r10, [r6]
101 ldr r6, PLL2_CTL
103 ldr r8, [r6]
107 str r8, [r6]
112 str r8, [r6]
117 str r8, [r6]
128 str r8, [r6]
133 str r8, [r6]
138 str r8, [r6]
141 ldr r6, PLL2_PLLM
143 str r2, [r6]
146 ldr r6, PLL2_DIV2
148 str r3, [r6]
151 ldr r6, PLL2_DIV1
153 str r4, [r6]
157 ldr r6, PLL2_DIV2
158 ldr r9, [r6]
163 str r8, [r6]
166 ldr r6, PLL2_PLLCMD
167 ldr r7, [r6]
169 str r7, [r6]
172 ldr r6, PLL2_PLLSTAT
174 ldr r7, [r6]
180 ldr r6, PLL2_DIV1
181 ldr r9, [r6]
186 str r8, [r6]
189 ldr r6, PLL2_PLLCMD
190 ldr r7, [r6]
192 str r7, [r6]
195 ldr r6, PLL2_PLLSTAT
197 ldr r7, [r6]
208 ldr r6, PLL2_CTL
209 ldr r8, [r6]
211 str r8, [r6]
220 ldr r6, PLL2_CTL
221 ldr r8, [r6]
223 str r8, [r6]
231 ldr r6, MDCTL_DDR2
232 ldr r7, [r6]
235 str r7, [r6]
238 ldr r6, PTCMD
239 ldr r7, [r6]
241 str r7, [r6]
245 ldr r6, PTSTAT
246 ldr r7, [r6]
252 ldr r6, MDSTAT_DDR2
253 ldr r7, [r6]
263 ldr r6, DDRCTL
265 str r7, [r6]
268 ldr r6, SDCFG
270 str r7, [r6]
273 ldr r6, SDTIM0
275 str r7, [r6]
278 ldr r6, SDTIM1
280 str r7, [r6]
290 ldr r6, SDREF
292 str r7, [r6]
306 ldr r6, MDCTL_DDR2
307 ldr r7, [r6]
310 str r7, [r6]
313 ldr r6, PTCMD
314 ldr r7, [r6]
316 str r7, [r6]
320 ldr r6, PTSTAT
321 ldr r7, [r6]
327 ldr r6, MDSTAT_DDR2
328 ldr r7, [r6]
338 ldr r6, MDCTL_DDR2
339 ldr r7, [r6]
341 str r7, [r6]
344 ldr r6, PTCMD
345 ldr r7, [r6]
347 str r7, [r6]
351 ldr r6, PTSTAT
352 ldr r7, [r6]
358 ldr r6, MDSTAT_DDR2
359 ldr r7, [r6]
365 ldr r6, CFGTEST
367 str r3, [r6]
375 ldr r6, PLL1_CTL
377 ldr r8, [r6]
381 str r8, [r6]
386 str r8, [r6]
391 str r8, [r6]
403 str r8, [r6]
407 str r8, [r6]
412 str r8, [r6]
417 str r8, [r6]
420 ldr r6, PLL1_PLLM
422 str r3, [r6]
432 ldr r6, PLL1_CTL
434 str r8, [r6]
445 str r8, [r6]
500 ldr r6, DFT_ENABLE
502 str r10, [r6]
504 ldr r6, DDRVTPR
505 ldr r7, [r6]
526 ldr r6, DFT_ENABLE
528 str r10, [r6]