Lines Matching refs:reg
29 u32 reg; in enable_ocotp_clk() local
31 reg = __raw_readl(&imx_ccm->CCGR2); in enable_ocotp_clk()
33 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK; in enable_ocotp_clk()
35 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK; in enable_ocotp_clk()
36 __raw_writel(reg, &imx_ccm->CCGR2); in enable_ocotp_clk()
83 u32 reg; in enable_usboh3_clk() local
85 reg = __raw_readl(&imx_ccm->CCGR6); in enable_usboh3_clk()
87 reg |= MXC_CCM_CCGR6_USBOH3_MASK; in enable_usboh3_clk()
89 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK); in enable_usboh3_clk()
90 __raw_writel(reg, &imx_ccm->CCGR6); in enable_usboh3_clk()
156 u32 reg; in enable_i2c_clk() local
166 reg = __raw_readl(&imx_ccm->CCGR2); in enable_i2c_clk()
168 reg |= mask; in enable_i2c_clk()
170 reg &= ~mask; in enable_i2c_clk()
171 __raw_writel(reg, &imx_ccm->CCGR2); in enable_i2c_clk()
182 reg = __raw_readl(addr); in enable_i2c_clk()
184 reg |= mask; in enable_i2c_clk()
186 reg &= ~mask; in enable_i2c_clk()
187 __raw_writel(reg, addr); in enable_i2c_clk()
196 u32 reg; in enable_spi_clk() local
203 reg = __raw_readl(&imx_ccm->CCGR1); in enable_spi_clk()
205 reg |= mask; in enable_spi_clk()
207 reg &= ~mask; in enable_spi_clk()
208 __raw_writel(reg, &imx_ccm->CCGR1); in enable_spi_clk()
310 u32 reg, freq; in get_mcu_main_clk() local
312 reg = __raw_readl(&imx_ccm->cacrr); in get_mcu_main_clk()
313 reg &= MXC_CCM_CACRR_ARM_PODF_MASK; in get_mcu_main_clk()
314 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET; in get_mcu_main_clk()
317 return freq / (reg + 1); in get_mcu_main_clk()
322 u32 reg, div = 0, freq = 0; in get_periph_clk() local
324 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
325 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { in get_periph_clk()
326 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> in get_periph_clk()
328 reg = __raw_readl(&imx_ccm->cbcmr); in get_periph_clk()
329 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK; in get_periph_clk()
330 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET; in get_periph_clk()
332 switch (reg) { in get_periph_clk()
344 reg = __raw_readl(&imx_ccm->cbcmr); in get_periph_clk()
345 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK; in get_periph_clk()
346 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET; in get_periph_clk()
348 switch (reg) { in get_periph_clk()
372 u32 reg, ipg_podf; in get_ipg_clk() local
374 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
375 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK; in get_ipg_clk()
376 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET; in get_ipg_clk()
383 u32 reg, perclk_podf; in get_ipg_per_clk() local
385 reg = __raw_readl(&imx_ccm->cscmr1); in get_ipg_per_clk()
388 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) in get_ipg_per_clk()
392 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK; in get_ipg_per_clk()
399 u32 reg, uart_podf; in get_uart_clk() local
401 reg = __raw_readl(&imx_ccm->cscdr1); in get_uart_clk()
405 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) in get_uart_clk()
409 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; in get_uart_clk()
410 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET; in get_uart_clk()
417 u32 reg, cspi_podf; in get_cspi_clk() local
419 reg = __raw_readl(&imx_ccm->cscdr2); in get_cspi_clk()
420 cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >> in get_cspi_clk()
425 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK) in get_cspi_clk()
554 u32 reg = 0; in enable_pll_video() local
598 reg = readl(&imx_ccm->analog_pll_video); in enable_pll_video()
599 if (reg & BM_ANADIG_PLL_VIDEO_LOCK) { in enable_pll_video()
619 u32 reg = 0; in mxs_set_lcdclk() local
638 reg = readl(&imx_ccm->cscdr2); in mxs_set_lcdclk()
640 if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0) in mxs_set_lcdclk()
646 reg = readl(&imx_ccm->cscdr2); in mxs_set_lcdclk()
648 if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0) in mxs_set_lcdclk()
771 u32 reg = 0; in enable_lcdif_clock() local
803 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
804 reg &= ~(MXC_CCM_CCGR3_LCDIF_AXI_MASK | in enable_lcdif_clock()
806 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
809 reg = readl(&imx_ccm->cscdr3); in enable_lcdif_clock()
810 reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK; in enable_lcdif_clock()
811 reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET; in enable_lcdif_clock()
812 writel(reg, &imx_ccm->cscdr3); in enable_lcdif_clock()
814 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
815 reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK | in enable_lcdif_clock()
817 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
826 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
827 reg &= ~lcdif_ccgr3_mask; in enable_lcdif_clock()
828 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
830 reg = readl(&imx_ccm->CCGR2); in enable_lcdif_clock()
831 reg &= ~MXC_CCM_CCGR2_LCD_MASK; in enable_lcdif_clock()
832 writel(reg, &imx_ccm->CCGR2); in enable_lcdif_clock()
836 reg = readl(&imx_ccm->cscdr2); in enable_lcdif_clock()
837 reg &= ~lcdif_clk_sel_mask; in enable_lcdif_clock()
838 writel(reg, &imx_ccm->cscdr2); in enable_lcdif_clock()
841 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
842 reg |= lcdif_ccgr3_mask; in enable_lcdif_clock()
843 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
845 reg = readl(&imx_ccm->CCGR2); in enable_lcdif_clock()
846 reg |= MXC_CCM_CCGR2_LCD_MASK; in enable_lcdif_clock()
847 writel(reg, &imx_ccm->CCGR2); in enable_lcdif_clock()
858 u32 reg = 0; in enable_qspi_clk() local
866 reg = readl(&imx_ccm->cscmr1); in enable_qspi_clk()
867 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK | in enable_qspi_clk()
869 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) | in enable_qspi_clk()
871 writel(reg, &imx_ccm->cscmr1); in enable_qspi_clk()
886 reg = readl(&imx_ccm->cs2cdr); in enable_qspi_clk()
887 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | in enable_qspi_clk()
890 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) | in enable_qspi_clk()
892 writel(reg, &imx_ccm->cs2cdr); in enable_qspi_clk()
907 u32 reg = 0; in enable_fec_anatop_clock() local
916 reg = readl(&anatop->pll_enet); in enable_fec_anatop_clock()
919 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; in enable_fec_anatop_clock()
920 reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq); in enable_fec_anatop_clock()
925 reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT; in enable_fec_anatop_clock()
926 reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq); in enable_fec_anatop_clock()
931 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || in enable_fec_anatop_clock()
932 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { in enable_fec_anatop_clock()
933 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN; in enable_fec_anatop_clock()
934 writel(reg, &anatop->pll_enet); in enable_fec_anatop_clock()
945 reg |= BM_ANADIG_PLL_ENET_ENABLE; in enable_fec_anatop_clock()
947 reg |= BM_ANADIG_PLL_ENET2_ENABLE; in enable_fec_anatop_clock()
948 reg &= ~BM_ANADIG_PLL_ENET_BYPASS; in enable_fec_anatop_clock()
949 writel(reg, &anatop->pll_enet); in enable_fec_anatop_clock()
953 reg = readl(&imx_ccm->CCGR3); in enable_fec_anatop_clock()
954 reg &= ~MXC_CCM_CCGR3_ENET_MASK; in enable_fec_anatop_clock()
955 writel(reg, &imx_ccm->CCGR3); in enable_fec_anatop_clock()
961 reg = readl(&imx_ccm->chsccdr); in enable_fec_anatop_clock()
962 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK in enable_fec_anatop_clock()
966 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET); in enable_fec_anatop_clock()
968 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET); in enable_fec_anatop_clock()
969 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET); in enable_fec_anatop_clock()
970 writel(reg, &imx_ccm->chsccdr); in enable_fec_anatop_clock()
973 reg = readl(&imx_ccm->CCGR3); in enable_fec_anatop_clock()
974 reg |= MXC_CCM_CCGR3_ENET_MASK; in enable_fec_anatop_clock()
975 writel(reg, &imx_ccm->CCGR3); in enable_fec_anatop_clock()
1050 u32 reg = 0; in enable_enet_pll() local
1053 reg = readl(&imx_ccm->analog_pll_enet); in enable_enet_pll()
1054 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN; in enable_enet_pll()
1055 writel(reg, &imx_ccm->analog_pll_enet); in enable_enet_pll()
1056 reg |= BM_ANADIG_PLL_SYS_ENABLE; in enable_enet_pll()
1063 reg &= ~BM_ANADIG_PLL_SYS_BYPASS; in enable_enet_pll()
1064 writel(reg, &imx_ccm->analog_pll_enet); in enable_enet_pll()
1065 reg |= en; in enable_enet_pll()
1066 writel(reg, &imx_ccm->analog_pll_enet); in enable_enet_pll()
1158 u32 reg; in hab_caam_clock_enable() local
1162 reg = __raw_readl(&imx_ccm->CCGR0); in hab_caam_clock_enable()
1164 reg |= MXC_CCM_CCGR0_DCP_CLK_MASK; in hab_caam_clock_enable()
1166 reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK; in hab_caam_clock_enable()
1167 __raw_writel(reg, &imx_ccm->CCGR0); in hab_caam_clock_enable()
1170 reg = __raw_readl(&imx_ccm->CCGR0); in hab_caam_clock_enable()
1172 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | in hab_caam_clock_enable()
1176 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | in hab_caam_clock_enable()
1179 __raw_writel(reg, &imx_ccm->CCGR0); in hab_caam_clock_enable()
1183 reg = __raw_readl(&imx_ccm->CCGR6); in hab_caam_clock_enable()
1185 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK; in hab_caam_clock_enable()
1187 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK; in hab_caam_clock_enable()
1188 __raw_writel(reg, &imx_ccm->CCGR6); in hab_caam_clock_enable()
1225 u32 reg; in enable_eim_clk() local
1227 reg = __raw_readl(&imx_ccm->CCGR6); in enable_eim_clk()
1229 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK; in enable_eim_clk()
1231 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK; in enable_eim_clk()
1232 __raw_writel(reg, &imx_ccm->CCGR6); in enable_eim_clk()
1318 int reg; in enable_ipu_clock() local
1319 reg = readl(&mxc_ccm->CCGR3); in enable_ipu_clock()
1320 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; in enable_ipu_clock()
1321 writel(reg, &mxc_ccm->CCGR3); in enable_ipu_clock()
1335 int reg; in disable_ldb_di_clock_sources() local
1338 reg = readl(&mxc_ccm->analog_pfd_528); in disable_ldb_di_clock_sources()
1341 reg |= 0x80008080; in disable_ldb_di_clock_sources()
1343 reg |= 0x80808080; in disable_ldb_di_clock_sources()
1344 writel(reg, &mxc_ccm->analog_pfd_528); in disable_ldb_di_clock_sources()
1347 reg = readl(&mxc_ccm->analog_pfd_480); in disable_ldb_di_clock_sources()
1348 reg |= 0x80808080; in disable_ldb_di_clock_sources()
1349 writel(reg, &mxc_ccm->analog_pfd_480); in disable_ldb_di_clock_sources()
1352 reg = readl(&mxc_ccm->analog_pll_video); in disable_ldb_di_clock_sources()
1353 reg &= ~(1 << 13); in disable_ldb_di_clock_sources()
1354 writel(reg, &mxc_ccm->analog_pll_video); in disable_ldb_di_clock_sources()
1360 int reg; in enable_ldb_di_clock_sources() local
1362 reg = readl(&mxc_ccm->analog_pfd_528); in enable_ldb_di_clock_sources()
1364 reg &= ~(0x80008080); in enable_ldb_di_clock_sources()
1366 reg &= ~(0x80808080); in enable_ldb_di_clock_sources()
1367 writel(reg, &mxc_ccm->analog_pfd_528); in enable_ldb_di_clock_sources()
1369 reg = readl(&mxc_ccm->analog_pfd_480); in enable_ldb_di_clock_sources()
1370 reg &= ~(0x80808080); in enable_ldb_di_clock_sources()
1371 writel(reg, &mxc_ccm->analog_pfd_480); in enable_ldb_di_clock_sources()
1381 int reg; in select_ldb_di_clock_source() local
1408 reg = readl(&mxc_ccm->ccdr); in select_ldb_di_clock_source()
1409 reg |= MXC_CCM_CCDR_MMDC_CH1_HS_MASK; in select_ldb_di_clock_source()
1410 writel(reg, &mxc_ccm->ccdr); in select_ldb_di_clock_source()
1413 reg = readl(&mxc_ccm->cbcmr); in select_ldb_di_clock_source()
1414 reg &= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL; in select_ldb_di_clock_source()
1415 writel(reg, &mxc_ccm->cbcmr); in select_ldb_di_clock_source()
1421 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1422 reg |= MXC_CCM_CBCDR_PERIPH2_CLK_SEL; in select_ldb_di_clock_source()
1423 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1429 reg = readl(&mxc_ccm->ccsr); in select_ldb_di_clock_source()
1430 reg |= MXC_CCM_CCSR_PLL3_SW_CLK_SEL; in select_ldb_di_clock_source()
1431 writel(reg, &mxc_ccm->ccsr); in select_ldb_di_clock_source()
1434 reg = readl(&mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1435 reg |= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET) in select_ldb_di_clock_source()
1437 writel(reg, &mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1440 reg = readl(&mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1441 reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK in select_ldb_di_clock_source()
1443 reg |= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET) in select_ldb_di_clock_source()
1445 writel(reg, &mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1448 reg = readl(&mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1449 reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK in select_ldb_di_clock_source()
1451 reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET) in select_ldb_di_clock_source()
1453 writel(reg, &mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1456 reg = readl(&mxc_ccm->ccsr); in select_ldb_di_clock_source()
1457 reg &= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL; in select_ldb_di_clock_source()
1458 writel(reg, &mxc_ccm->ccsr); in select_ldb_di_clock_source()
1464 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1465 reg &= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL; in select_ldb_di_clock_source()
1466 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1472 reg = readl(&mxc_ccm->ccdr); in select_ldb_di_clock_source()
1473 reg &= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK; in select_ldb_di_clock_source()
1474 writel(reg, &mxc_ccm->ccdr); in select_ldb_di_clock_source()