67 	clock_enable(CCGR_OCOTP, enable);  in enable_ocotp_clk()
82 		clock_enable(CCGR_USB_HSIC, 0);  in enable_usboh3_clk()
92 		clock_enable(CCGR_USB_CTRL, 1);  in enable_usboh3_clk()
93 		clock_enable(CCGR_USB_HSIC, 1);  in enable_usboh3_clk()
94 		clock_enable(CCGR_USB_PHY1, 1);  in enable_usboh3_clk()
95 		clock_enable(CCGR_USB_PHY2, 1);  in enable_usboh3_clk()
97 		clock_enable(CCGR_USB_CTRL, 0);  in enable_usboh3_clk()
98 		clock_enable(CCGR_USB_HSIC, 0);  in enable_usboh3_clk()
99 		clock_enable(CCGR_USB_PHY1, 0);  in enable_usboh3_clk()
100 		clock_enable(CCGR_USB_PHY2, 0);  in enable_usboh3_clk()
532 		clock_enable(CCGR_I2C1 + i2c_num, 0);  in enable_i2c_clk()
542 		clock_enable(CCGR_I2C1 + i2c_num, 1);  in enable_i2c_clk()
544 		clock_enable(CCGR_I2C1 + i2c_num, 0);  in enable_i2c_clk()
556 	clock_enable(CCGR_USDHC1, 0);  in init_clk_esdhc()
557 	clock_enable(CCGR_USDHC2, 0);  in init_clk_esdhc()
558 	clock_enable(CCGR_USDHC3, 0);  in init_clk_esdhc()
577 	clock_enable(CCGR_USDHC1, 1);  in init_clk_esdhc()
578 	clock_enable(CCGR_USDHC2, 1);  in init_clk_esdhc()
579 	clock_enable(CCGR_USDHC3, 1);  in init_clk_esdhc()
587 	clock_enable(CCGR_UART1, 0);  in init_clk_uart()
588 	clock_enable(CCGR_UART2, 0);  in init_clk_uart()
589 	clock_enable(CCGR_UART3, 0);  in init_clk_uart()
590 	clock_enable(CCGR_UART4, 0);  in init_clk_uart()
591 	clock_enable(CCGR_UART5, 0);  in init_clk_uart()
592 	clock_enable(CCGR_UART6, 0);  in init_clk_uart()
593 	clock_enable(CCGR_UART7, 0);  in init_clk_uart()
632 	clock_enable(CCGR_UART1, 1);  in init_clk_uart()
633 	clock_enable(CCGR_UART2, 1);  in init_clk_uart()
634 	clock_enable(CCGR_UART3, 1);  in init_clk_uart()
635 	clock_enable(CCGR_UART4, 1);  in init_clk_uart()
636 	clock_enable(CCGR_UART5, 1);  in init_clk_uart()
637 	clock_enable(CCGR_UART6, 1);  in init_clk_uart()
638 	clock_enable(CCGR_UART7, 1);  in init_clk_uart()
646 	clock_enable(CCGR_WEIM, 0);  in init_clk_weim()
655 	clock_enable(CCGR_WEIM, 1);  in init_clk_weim()
663 	clock_enable(CCGR_ECSPI1, 0);  in init_clk_ecspi()
664 	clock_enable(CCGR_ECSPI2, 0);  in init_clk_ecspi()
665 	clock_enable(CCGR_ECSPI3, 0);  in init_clk_ecspi()
666 	clock_enable(CCGR_ECSPI4, 0);  in init_clk_ecspi()
690 	clock_enable(CCGR_ECSPI1, 1);  in init_clk_ecspi()
691 	clock_enable(CCGR_ECSPI2, 1);  in init_clk_ecspi()
692 	clock_enable(CCGR_ECSPI3, 1);  in init_clk_ecspi()
693 	clock_enable(CCGR_ECSPI4, 1);  in init_clk_ecspi()
701 	clock_enable(CCGR_WDOG1, 0);  in init_clk_wdog()
702 	clock_enable(CCGR_WDOG2, 0);  in init_clk_wdog()
703 	clock_enable(CCGR_WDOG3, 0);  in init_clk_wdog()
704 	clock_enable(CCGR_WDOG4, 0);  in init_clk_wdog()
713 	clock_enable(CCGR_WDOG1, 1);  in init_clk_wdog()
714 	clock_enable(CCGR_WDOG2, 1);  in init_clk_wdog()
715 	clock_enable(CCGR_WDOG3, 1);  in init_clk_wdog()
716 	clock_enable(CCGR_WDOG4, 1);  in init_clk_wdog()
725 	clock_enable(CCGR_EPDC, 0);  in init_clk_epdc()
734 	clock_enable(CCGR_EPDC, 1);  in init_clk_epdc()
857 	clock_enable(CCGR_QSPI, 0);  in set_clk_qspi()
866 	clock_enable(CCGR_QSPI, 1);  in set_clk_qspi()
876 	clock_enable(CCGR_RAWNAND, 0);  in set_clk_nand()
886 	clock_enable(CCGR_RAWNAND, 1);  in set_clk_nand()
903 	clock_enable(CCGR_LCDIF, 0);  in mxs_set_lcdclk()
953 	clock_enable(CCGR_LCDIF, 1);  in mxs_set_lcdclk()
964 	clock_enable(CCGR_ENET1, 0);  in set_clk_enet()
965 	clock_enable(CCGR_ENET2, 0);  in set_clk_enet()
1022 	clock_enable(CCGR_ENET1, 1);  in set_clk_enet()
1023 	clock_enable(CCGR_ENET2, 1);  in set_clk_enet()
1064 	clock_enable(CCGR_SNVS, 1);  in clock_init()
1067 	clock_enable(CCGR_RAWNAND, 1);  in clock_init()
1071 		clock_enable(CCGR_RDC, 1);  in clock_init()
1072 		clock_enable(CCGR_SEMA1, 1);  in clock_init()
1073 		clock_enable(CCGR_SEMA2, 1);  in clock_init()
1081 		clock_enable(CCGR_CAAM, 1);  in hab_caam_clock_enable()
1083 		clock_enable(CCGR_CAAM, 0);  in hab_caam_clock_enable()
1090 	clock_enable(CCGR_EPDC, 1);  in epdc_clock_enable()
1094 	clock_enable(CCGR_EPDC, 0);  in epdc_clock_disable()