Lines Matching refs:base
24 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) in ddr3_init_ddrphy() argument
28 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) in ddr3_init_ddrphy()
32 __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET); in ddr3_init_ddrphy()
34 tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET); in ddr3_init_ddrphy()
37 __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET); in ddr3_init_ddrphy()
39 __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET); in ddr3_init_ddrphy()
40 __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET); in ddr3_init_ddrphy()
41 __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET); in ddr3_init_ddrphy()
42 __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET); in ddr3_init_ddrphy()
44 tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET); in ddr3_init_ddrphy()
47 __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET); in ddr3_init_ddrphy()
49 __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET); in ddr3_init_ddrphy()
50 __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET); in ddr3_init_ddrphy()
51 __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET); in ddr3_init_ddrphy()
52 __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET); in ddr3_init_ddrphy()
53 __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET); in ddr3_init_ddrphy()
54 __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET); in ddr3_init_ddrphy()
55 __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET); in ddr3_init_ddrphy()
56 __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET); in ddr3_init_ddrphy()
58 __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET); in ddr3_init_ddrphy()
59 __raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET); in ddr3_init_ddrphy()
60 __raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET); in ddr3_init_ddrphy()
62 __raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET); in ddr3_init_ddrphy()
63 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) in ddr3_init_ddrphy()
67 clrsetbits_le32(base + KS2_DDRPHY_DATX8_2_OFFSET, in ddr3_init_ddrphy()
71 clrsetbits_le32(base + KS2_DDRPHY_DATX8_3_OFFSET, in ddr3_init_ddrphy()
75 clrsetbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, in ddr3_init_ddrphy()
79 clrsetbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, in ddr3_init_ddrphy()
83 clrsetbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, in ddr3_init_ddrphy()
87 clrsetbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, in ddr3_init_ddrphy()
91 clrsetbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, in ddr3_init_ddrphy()
96 __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET); in ddr3_init_ddrphy()
97 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) in ddr3_init_ddrphy()
101 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) in ddr3_init_ddremif() argument
103 __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET); in ddr3_init_ddremif()
104 __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET); in ddr3_init_ddremif()
105 __raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET); in ddr3_init_ddremif()
106 __raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET); in ddr3_init_ddremif()
107 __raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET); in ddr3_init_ddremif()
108 __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET); in ddr3_init_ddremif()
109 __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET); in ddr3_init_ddremif()
112 int ddr3_ecc_support_rmw(u32 base) in ddr3_ecc_support_rmw() argument
114 u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET); in ddr3_ecc_support_rmw()
124 static void ddr3_ecc_config(u32 base, u32 value) in ddr3_ecc_config() argument
128 __raw_writel(value, base + KS2_DDR3_ECC_CTRL_OFFSET); in ddr3_ecc_config()
133 data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); in ddr3_ecc_config()
134 __raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); in ddr3_ecc_config()
139 base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET); in ddr3_ecc_config()
144 base + KS2_DDR3_ECC_INT_STATUS_OFFSET); in ddr3_ecc_config()
148 static void ddr3_reset_data(u32 base, u32 ddr3_size) in ddr3_reset_data() argument
197 base >> KS2_MSMC_SEG_SIZE_SHIFT, in ddr3_reset_data()
202 base >> KS2_MSMC_SEG_SIZE_SHIFT, in ddr3_reset_data()
216 for (dst = base, blks = 0; blks < edma_blks; in ddr3_reset_data()
238 static void ddr3_ecc_init_range(u32 base) in ddr3_ecc_init_range() argument
241 u32 rmw = ddr3_ecc_support_rmw(base); in ddr3_ecc_init_range()
246 __raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET); in ddr3_ecc_init_range()
248 ddr3_ecc_config(base, ecc_val); in ddr3_ecc_init_range()
251 void ddr3_enable_ecc(u32 base, int test) in ddr3_enable_ecc() argument
254 u32 rmw = ddr3_ecc_support_rmw(base); in ddr3_enable_ecc()
268 ddr3_ecc_config(base, ecc_val); in ddr3_enable_ecc()
271 void ddr3_disable_ecc(u32 base) in ddr3_disable_ecc() argument
273 ddr3_ecc_config(base, 0); in ddr3_disable_ecc()
277 static void cic_init(u32 base) in cic_init() argument
280 __raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE); in cic_init()
283 __raw_writel(0, base + KS2_CIC_CTRL); in cic_init()
284 __raw_writel(0, base + KS2_CIC_HOST_CTRL); in cic_init()
287 __raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE); in cic_init()
290 static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num) in cic_map_cic_to_gic() argument
293 __raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num); in cic_map_cic_to_gic()
296 __raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET); in cic_map_cic_to_gic()
299 __raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET); in cic_map_cic_to_gic()
302 static void ddr3_map_ecc_cic2_irq(u32 base) in ddr3_map_ecc_cic2_irq() argument
304 cic_init(base); in ddr3_map_ecc_cic2_irq()
305 cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM, in ddr3_map_ecc_cic2_irq()
310 void ddr3_init_ecc(u32 base, u32 ddr3_size) in ddr3_init_ecc() argument
312 if (!ddr3_ecc_support_rmw(base)) { in ddr3_init_ecc()
313 ddr3_disable_ecc(base); in ddr3_init_ecc()
317 ddr3_ecc_init_range(base); in ddr3_init_ecc()
324 ddr3_enable_ecc(base, 0); in ddr3_init_ecc()
327 void ddr3_check_ecc_int(u32 base) in ddr3_check_ecc_int() argument
331 u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET); in ddr3_check_ecc_int()
349 value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); in ddr3_check_ecc_int()
352 value = __raw_readl(base + in ddr3_check_ecc_int()