Lines Matching refs:nr
38 static inline u32 get_mr(int nr, u32 cs, u32 mr_addr) in get_mr() argument
43 writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); in get_mr()
45 mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data); in get_mr()
55 static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val) in set_mr() argument
58 writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); in set_mr()
59 writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data); in set_mr()
62 static void configure_mr(int nr, u32 cs) in configure_mr() argument
66 while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) in configure_mr()
68 set_mr(nr, cs, LPDDR2_MR10, 0x56); in configure_mr()
70 set_mr(nr, cs, LPDDR2_MR1, 0x43); in configure_mr()
71 set_mr(nr, cs, LPDDR2_MR2, 0x2); in configure_mr()
74 set_mr(nr, cs, mr_addr, 0x2); in configure_mr()
81 void config_sdram_emif4d5(const struct emif_regs *regs, int nr) in config_sdram_emif4d5() argument
83 writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl); in config_sdram_emif4d5()
84 writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw); in config_sdram_emif4d5()
85 writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); in config_sdram_emif4d5()
87 writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config); in config_sdram_emif4d5()
89 &emif_reg[nr]->emif_rd_wr_lvl_rmp_win); in config_sdram_emif4d5()
91 &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl); in config_sdram_emif4d5()
92 writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl); in config_sdram_emif4d5()
94 &emif_reg[nr]->emif_rd_wr_exec_thresh); in config_sdram_emif4d5()
102 writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map); in config_sdram_emif4d5()
103 writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map); in config_sdram_emif4d5()
104 writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map); in config_sdram_emif4d5()
105 writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config); in config_sdram_emif4d5()
113 writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); in config_sdram_emif4d5()
114 writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc); in config_sdram_emif4d5()
115 writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); in config_sdram_emif4d5()
117 clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl, in config_sdram_emif4d5()
120 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); in config_sdram_emif4d5()
126 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); in config_sdram_emif4d5()
127 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); in config_sdram_emif4d5()
131 writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) | in config_sdram_emif4d5()
132 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); in config_sdram_emif4d5()
133 writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) | in config_sdram_emif4d5()
134 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw); in config_sdram_emif4d5()
136 writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl); in config_sdram_emif4d5()
139 writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl); in config_sdram_emif4d5()
145 while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000) in config_sdram_emif4d5()
150 if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0) in config_sdram_emif4d5()
155 configure_mr(nr, 0); in config_sdram_emif4d5()
156 configure_mr(nr, 1); in config_sdram_emif4d5()
163 void config_sdram(const struct emif_regs *regs, int nr) in config_sdram() argument
166 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); in config_sdram()
167 writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1); in config_sdram()
168 writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw); in config_sdram()
169 writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* initially a large refresh period */ in config_sdram()
170 writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* trigger initialization */ in config_sdram()
171 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); in config_sdram()
174 writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); in config_sdram()
176 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); in config_sdram()
179 writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl); in config_sdram()
184 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); in config_sdram()
185 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); in config_sdram()
187 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); in config_sdram()
188 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); in config_sdram()
189 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); in config_sdram()
193 writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config); in config_sdram()
200 void set_sdram_timings(const struct emif_regs *regs, int nr) in set_sdram_timings() argument
202 writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1); in set_sdram_timings()
203 writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw); in set_sdram_timings()
204 writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2); in set_sdram_timings()
205 writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw); in set_sdram_timings()
206 writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3); in set_sdram_timings()
207 writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw); in set_sdram_timings()
213 static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr) in ext_phy_settings_swlvl() argument
223 (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); in ext_phy_settings_swlvl()
253 static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr) in ext_phy_settings_hwlvl() argument
259 writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); in ext_phy_settings_hwlvl()
260 writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw); in ext_phy_settings_hwlvl()
261 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22); in ext_phy_settings_hwlvl()
262 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw); in ext_phy_settings_hwlvl()
263 writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23); in ext_phy_settings_hwlvl()
264 writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw); in ext_phy_settings_hwlvl()
265 writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24); in ext_phy_settings_hwlvl()
266 writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw); in ext_phy_settings_hwlvl()
267 writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25); in ext_phy_settings_hwlvl()
268 writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw); in ext_phy_settings_hwlvl()
269 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26); in ext_phy_settings_hwlvl()
270 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw); in ext_phy_settings_hwlvl()
271 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27); in ext_phy_settings_hwlvl()
272 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw); in ext_phy_settings_hwlvl()
273 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28); in ext_phy_settings_hwlvl()
274 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw); in ext_phy_settings_hwlvl()
275 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29); in ext_phy_settings_hwlvl()
276 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw); in ext_phy_settings_hwlvl()
277 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30); in ext_phy_settings_hwlvl()
278 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw); in ext_phy_settings_hwlvl()
279 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31); in ext_phy_settings_hwlvl()
280 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw); in ext_phy_settings_hwlvl()
281 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32); in ext_phy_settings_hwlvl()
282 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw); in ext_phy_settings_hwlvl()
283 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33); in ext_phy_settings_hwlvl()
284 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw); in ext_phy_settings_hwlvl()
285 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34); in ext_phy_settings_hwlvl()
286 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw); in ext_phy_settings_hwlvl()
287 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35); in ext_phy_settings_hwlvl()
288 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw); in ext_phy_settings_hwlvl()
289 writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); in ext_phy_settings_hwlvl()
290 writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw); in ext_phy_settings_hwlvl()
296 writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); in ext_phy_settings_hwlvl()
297 writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc); in ext_phy_settings_hwlvl()
298 writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); in ext_phy_settings_hwlvl()
304 void config_ddr_phy(const struct emif_regs *regs, int nr) in config_ddr_phy() argument
314 &emif_reg[nr]->emif_sdram_ref_ctrl); in config_ddr_phy()
317 &emif_reg[nr]->emif_ddr_phy_ctrl_1); in config_ddr_phy()
319 &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw); in config_ddr_phy()
321 if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) { in config_ddr_phy()
323 ext_phy_settings_hwlvl(regs, nr); in config_ddr_phy()
325 ext_phy_settings_swlvl(regs, nr); in config_ddr_phy()
332 void config_cmd_ctrl(const struct cmd_control *cmd, int nr) in config_cmd_ctrl() argument
337 writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio); in config_cmd_ctrl()
338 writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout); in config_cmd_ctrl()
340 writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio); in config_cmd_ctrl()
341 writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout); in config_cmd_ctrl()
343 writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio); in config_cmd_ctrl()
344 writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout); in config_cmd_ctrl()
350 void config_ddr_data(const struct ddr_data *data, int nr) in config_ddr_data() argument
359 &(ddr_data_reg[nr]+i)->dt0rdsratio0); in config_ddr_data()
361 &(ddr_data_reg[nr]+i)->dt0wdsratio0); in config_ddr_data()
363 &(ddr_data_reg[nr]+i)->dt0wiratio0); in config_ddr_data()
365 &(ddr_data_reg[nr]+i)->dt0giratio0); in config_ddr_data()
367 &(ddr_data_reg[nr]+i)->dt0fwsratio0); in config_ddr_data()
369 &(ddr_data_reg[nr]+i)->dt0wrsratio0); in config_ddr_data()