320 	u32 reg, clock;  in cm_get_main_vco_clk_hz()  local
324 	clock = cm_get_osc_clk_hz(1);  in cm_get_main_vco_clk_hz()
325 	clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>  in cm_get_main_vco_clk_hz()
327 	clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>  in cm_get_main_vco_clk_hz()
330 	return clock;  in cm_get_main_vco_clk_hz()
335 	u32 reg, clock = 0;  in cm_get_per_vco_clk_hz()  local
342 		clock = cm_get_osc_clk_hz(1);  in cm_get_per_vco_clk_hz()
344 		clock = cm_get_osc_clk_hz(2);  in cm_get_per_vco_clk_hz()
346 		clock = cm_get_f2s_per_ref_clk_hz();  in cm_get_per_vco_clk_hz()
350 	clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>  in cm_get_per_vco_clk_hz()
352 	clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>  in cm_get_per_vco_clk_hz()
355 	return clock;  in cm_get_per_vco_clk_hz()
360 	u32 reg, clock;  in cm_get_mpu_clk_hz()  local
362 	clock = cm_get_main_vco_clk_hz();  in cm_get_mpu_clk_hz()
366 	clock /= (reg + 1);  in cm_get_mpu_clk_hz()
368 	clock /= (reg + 1);  in cm_get_mpu_clk_hz()
369 	return clock;  in cm_get_mpu_clk_hz()
374 	u32 reg, clock = 0;  in cm_get_sdram_clk_hz()  local
381 		clock = cm_get_osc_clk_hz(1);  in cm_get_sdram_clk_hz()
383 		clock = cm_get_osc_clk_hz(2);  in cm_get_sdram_clk_hz()
385 		clock = cm_get_f2s_sdr_ref_clk_hz();  in cm_get_sdram_clk_hz()
389 	clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>  in cm_get_sdram_clk_hz()
391 	clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>  in cm_get_sdram_clk_hz()
398 	clock /= (reg + 1);  in cm_get_sdram_clk_hz()
400 	return clock;  in cm_get_sdram_clk_hz()
405 	u32 reg, clock = 0;  in cm_get_l4_sp_clk_hz()  local
413 		clock = cm_get_main_vco_clk_hz();  in cm_get_l4_sp_clk_hz()
417 		clock /= (reg + 1);  in cm_get_l4_sp_clk_hz()
419 		clock /= (reg + 1);  in cm_get_l4_sp_clk_hz()
421 		clock = cm_get_per_vco_clk_hz();  in cm_get_l4_sp_clk_hz()
425 		clock /= (reg + 1);  in cm_get_l4_sp_clk_hz()
432 	clock = clock / (1 << reg);  in cm_get_l4_sp_clk_hz()
434 	return clock;  in cm_get_l4_sp_clk_hz()
439 	u32 reg, clock = 0;  in cm_get_mmc_controller_clk_hz()  local
447 		clock = cm_get_f2s_per_ref_clk_hz();  in cm_get_mmc_controller_clk_hz()
449 		clock = cm_get_main_vco_clk_hz();  in cm_get_mmc_controller_clk_hz()
453 		clock /= (reg + 1);  in cm_get_mmc_controller_clk_hz()
455 		clock = cm_get_per_vco_clk_hz();  in cm_get_mmc_controller_clk_hz()
459 		clock /= (reg + 1);  in cm_get_mmc_controller_clk_hz()
463 	clock /= 4;  in cm_get_mmc_controller_clk_hz()
464 	return clock;  in cm_get_mmc_controller_clk_hz()
469 	u32 reg, clock = 0;  in cm_get_qspi_controller_clk_hz()  local
477 		clock = cm_get_f2s_per_ref_clk_hz();  in cm_get_qspi_controller_clk_hz()
479 		clock = cm_get_main_vco_clk_hz();  in cm_get_qspi_controller_clk_hz()
483 		clock /= (reg + 1);  in cm_get_qspi_controller_clk_hz()
485 		clock = cm_get_per_vco_clk_hz();  in cm_get_qspi_controller_clk_hz()
489 		clock /= (reg + 1);  in cm_get_qspi_controller_clk_hz()
492 	return clock;  in cm_get_qspi_controller_clk_hz()
497 	u32 reg, clock = 0;  in cm_get_spi_controller_clk_hz()  local
499 	clock = cm_get_per_vco_clk_hz();  in cm_get_spi_controller_clk_hz()
503 	clock /= (reg + 1);  in cm_get_spi_controller_clk_hz()
505 	return clock;  in cm_get_spi_controller_clk_hz()