23 	struct sunxi_ccm_reg * const ccm =  in clock_init_safe()  local
38 	       C0_CFG_APB0_CLK_DIV_RATIO(2), &ccm->c0_cfg);  in clock_init_safe()
42 	       &ccm->ahb0_cfg);  in clock_init_safe()
45 	       &ccm->ahb1_cfg);  in clock_init_safe()
48 	       &ccm->ahb2_cfg);  in clock_init_safe()
51 	       &ccm->apb0_cfg);  in clock_init_safe()
55 	       &ccm->gtbus_cfg);  in clock_init_safe()
58 	       &ccm->cci400_cfg);  in clock_init_safe()
61 	setbits_le32(&ccm->ahb_reset1_cfg, (1 << 24));  in clock_init_safe()
62 	setbits_le32(&ccm->apb1_gate, (1 << 24));  in clock_init_safe()
71 	struct sunxi_ccm_reg *const ccm =  in clock_init_uart()  local
75 	setbits_le32(&ccm->apb1_gate,  in clock_init_uart()
79 	setbits_le32(&ccm->apb1_reset_cfg,  in clock_init_uart()
87 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll1()  local
92 	clrsetbits_le32(&ccm->cpu_clk_source, C0_CPUX_CLK_SRC_MASK,  in clock_set_pll1()
98 	       &ccm->pll1_c0_cfg);  in clock_set_pll1()
108 	clrsetbits_le32(&ccm->cpu_clk_source, C0_CPUX_CLK_SRC_MASK,  in clock_set_pll1()
114 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll2()  local
119 	clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK,  in clock_set_pll2()
124 	       &ccm->pll2_c1_cfg);  in clock_set_pll2()
129 	clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK,  in clock_set_pll2()
135 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll6()  local
141 	       &ccm->pll6_ddr_cfg);  in clock_set_pll6()
142 	do { } while (!(readl(&ccm->pll_stable_status) & PLL_DDR_STATUS));  in clock_set_pll6()
149 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll12()  local
152 	if (readl(&ccm->pll12_periph1_cfg) & CCM_PLL12_CTRL_EN)  in clock_set_pll12()
156 	       &ccm->pll12_periph1_cfg);  in clock_set_pll12()
164 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll4()  local
168 	       &ccm->pll4_periph0_cfg);  in clock_set_pll4()
176 	struct sunxi_ccm_reg *const ccm =  in clock_twi_onoff()  local
184 		setbits_le32(&ccm->apb1_gate,  in clock_twi_onoff()
186 		setbits_le32(&ccm->apb1_reset_cfg,  in clock_twi_onoff()
189 		clrbits_le32(&ccm->apb1_reset_cfg,  in clock_twi_onoff()
191 		clrbits_le32(&ccm->apb1_gate,  in clock_twi_onoff()
200 	struct sunxi_ccm_reg *const ccm =  in clock_get_pll4_periph0()  local
202 	uint32_t rval = readl(&ccm->pll4_periph0_cfg);  in clock_get_pll4_periph0()