Lines Matching refs:mr
362 u16 mr[4] = { 0, }; in mctl_channel_init() local
460 mr[0] = DDR3_MR0_PPD_FAST_EXIT | DDR3_MR0_WR(tWR) | in mctl_channel_init()
462 mr[1] = DDR3_MR1_RTT120OHM; in mctl_channel_init()
463 mr[2] = DDR3_MR2_TWL(CWL); in mctl_channel_init()
464 mr[3] = 0; in mctl_channel_init()
483 writel(MCTL_INIT3_MR(mr[0]) | MCTL_INIT3_EMR(mr[1]), in mctl_channel_init()
485 writel(MCTL_INIT4_EMR2(mr[2]) | MCTL_INIT4_EMR3(mr[3]), in mctl_channel_init()
504 writel(MCTL_INIT3_MR(mr[1]) | MCTL_INIT3_EMR(mr[2]), in mctl_channel_init()
506 writel(MCTL_INIT4_EMR2(mr[3]), in mctl_channel_init()
632 writel(mr[0], &mctl_phy->mr0); in mctl_channel_init()
633 writel(mr[1], &mctl_phy->mr1); in mctl_channel_init()
634 writel(mr[2], &mctl_phy->mr2); in mctl_channel_init()
635 writel(mr[3], &mctl_phy->mr3); in mctl_channel_init()