62 	struct clk_rst_ctlr *clkrst =  in clock_get_osc_bypass()  local
66 	reg = readl(&clkrst->crc_osc_ctrl);  in clock_get_osc_bypass()
73 	struct clk_rst_ctlr *clkrst =  in get_pll()  local
81 	return &clkrst->crc_pll[clkid];  in get_pll()
512 	struct clk_rst_ctlr *clkrst =  in reset_cmplx_set_enable()  local
522 		writel(mask, &clkrst->crc_cpu_cmplx_set);  in reset_cmplx_set_enable()
524 		writel(mask, &clkrst->crc_cpu_cmplx_clr);  in reset_cmplx_set_enable()
724 	struct clk_rst_ctlr *clkrst =  in set_avp_clock_source()  local
733 	writel(val, &clkrst->crc_sclk_brst_pol);  in set_avp_clock_source()
744 	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;  in tegra30_set_up_pllp()  local
793 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);  in tegra30_set_up_pllp()
799 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);  in tegra30_set_up_pllp()
804 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);  in tegra30_set_up_pllp()
810 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);  in tegra30_set_up_pllp()