31 int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus)  in uniphier_ld4_ddrphy_init()  argument
48 	writel(0x0300c473, phy_base + PHY_PGCR1);  in uniphier_ld4_ddrphy_init()
49 	writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0);  in uniphier_ld4_ddrphy_init()
50 	writel(ddrphy_ptr1[freq_e], phy_base + PHY_PTR1);  in uniphier_ld4_ddrphy_init()
51 	writel(0x00083DEF, phy_base + PHY_PTR2);  in uniphier_ld4_ddrphy_init()
52 	writel(ddrphy_ptr3[freq_e], phy_base + PHY_PTR3);  in uniphier_ld4_ddrphy_init()
53 	writel(ddrphy_ptr4[freq_e], phy_base + PHY_PTR4);  in uniphier_ld4_ddrphy_init()
54 	writel(0xF004001A, phy_base + PHY_DSGCR);  in uniphier_ld4_ddrphy_init()
57 	tmp = readl(phy_base + PHY_DXCCR);  in uniphier_ld4_ddrphy_init()
60 	writel(tmp, phy_base + PHY_DXCCR);  in uniphier_ld4_ddrphy_init()
62 	writel(0x0000040B, phy_base + PHY_DCR);  in uniphier_ld4_ddrphy_init()
63 	writel(ddrphy_dtpr0[freq_e], phy_base + PHY_DTPR0);  in uniphier_ld4_ddrphy_init()
64 	writel(ddrphy_dtpr1[freq_e], phy_base + PHY_DTPR1);  in uniphier_ld4_ddrphy_init()
65 	writel(ddrphy_dtpr2[freq_e], phy_base + PHY_DTPR2);  in uniphier_ld4_ddrphy_init()
66 	writel(ddrphy_mr0[freq_e], phy_base + PHY_MR0);  in uniphier_ld4_ddrphy_init()
67 	writel(0x00000006, phy_base + PHY_MR1);  in uniphier_ld4_ddrphy_init()
68 	writel(ddrphy_mr2[freq_e], phy_base + PHY_MR2);  in uniphier_ld4_ddrphy_init()
69 	writel(ddr3plus ? 0x00000800 : 0x00000000, phy_base + PHY_MR3);  in uniphier_ld4_ddrphy_init()
71 	while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))  in uniphier_ld4_ddrphy_init()
74 	writel(0x0300C473, phy_base + PHY_PGCR1);  in uniphier_ld4_ddrphy_init()
75 	writel(0x0000005D, phy_base + PHY_ZQ_BASE + PHY_ZQ_CR1);  in uniphier_ld4_ddrphy_init()